Data translator and recording system for use with tone generating telephones

Claim 3

The system of claim 1 wherein each of said logic units further comprises a third capacitor connected in parallel with said resistor, second and third voltage sources, a second resistor interconnecting the base of said transistor with said second voltage source, and a third resistor interconnecting the collector of said transistor with said third voltage source.

Claim 4

The system of claim 1 wherein said translator further comprises a logic device responsive to said additional D.C. signal for causing electrical power to be applied to said data recording unit.

Claim 5

A data recording system comprising a telephone set having 12 keys, 10 of which are for manually generating 10 tone signals each representing a different one of the 10 numerals 0 through 9 and the other two of which are for manually generating 11th and 12th tone signals, a data set including seven output terminals first through seventh, for converting each of said tone signals into a pair of D.C. signals, one signal of each pair being applied to one of the output terminals fifth through seventh, the output terminals to which any pair of D.C. signals are applied being dependent upon the tone signal converted, said 11th tone signal causing application of D.C. signals to said fourth and fifth output terminals and said 12th tone signal causing application of D.C. signals to said fourth and seventh output terminals, a data recording unit including 12 input terminals and a buffer memory for recording data records, each record comprising a certain number of data fields, each field comprising one or more bits, said unit being responsive to electrical pulses applied to any one of 10 of said input terminals n1, ..., n10 for recording one of the numerals 0 through 9, responsive to an electrical signal applied to an eleventh one of said input terminals n11 for preparing to record data over any data record or portion thereof previously recorded in said memory, and responsive to an electrical signal applied to a twelfth one of said input terminals n12 for skipping to a next data field, and a translator comprising a plurality of logic units first through tenth each interconnecting selected pairs of said output terminals with a different one of said input terminals n1 through n10, one output terminal of each pair being one of the terminals first through fourth and the other output terminal of the pair being one of the terminals fifth through seventh, said logic units each including means responsive to D.C. signals applied to the two output terminals to which the logic unit is connected for applying an electrical pulse to the input terminal to which the logic unit is connected, said electrical pulse being of a fixed duration independent of the duration of said D.C. signals, said translator further comprising an eleventh logic unit interconnecting said fourth and fifth output terminals with said input terminal n11, and a 12th logic unit interconnecting said fourth and seventh output terminals with said input terminal n12, said 11th and 12th logic units each including means responsive to the D.C. signals applied to the two output terminals to which the logic unit is connected for generating and applying an electrical signal to the respective input terminal to which the logic unit is connected, said electrical signal being of a duration approximately equal to the duration of the D.C. signals in response to which the electrical signal is generated, the means of said 11th and 12th logic units comprising circuitry responsive to a pair of D.C. signals for generating an output signal and a transistor whose collector is connected to a corresponding one of said input terminals and whose base is connected to said output signal generating circuitry.

Claim 6

A data recording system comprising a telephone set having 12 keys, 10 of which are for manually generating 10 tone signals each representing a different one of the 10 numerals 0 through 9 and the other two of which are for manually generating 11th and 12th tone signals, a data set including seven output terminals first through seventh, for converting each of said tone signals into a pair of D.C. signals, one signal of each pair being applied to one of the output terminals fifth through seventh, the output terminals to which any pair of D.C. signals are applied being dependent upon the tone signal converted, said 11th tone signal causing application of D.C. signals to said fourth and fifth output terminals and said 12th tone signal causing application of D.C. signals to said fourth and seventh output terminals, a data recording unit including 12 input terminals and a buffer memory for recording data records, each record comprising a certain number of data fields, each field comprising one or more bits, said unit being responsive to electrical pulses applied to any one of 10 of said input terminals n1, ..., n10 for recording one of the numerals 0 through 9, responsive to an electrical signal applied to an eleventh one of said input terminals n11 for preparing to record data over any data record or portion thereof previously recorded in said memory, and responsive to an electrical signal applied to a twelfth one of said input terminals n12 for skipping to a next data field, and a translator comprising a plurality of logic units first through tenth each interconnecting selected pairs of said output terminals with a different one of said input terminals n1 through n10, one output terminal of each pair being one of the terminals first through fourth and the other output terminal of the pair being one of the terminals fifth through seventh, said logic units each including means responsive to D.C. signals applied to the two output terminals to which the logic unit is connected for applying an electrical pulse to the input terminal to which the logic unit is connected, said electrical pulse being of a fixed duration independent of the duration of said D.C. signals, said translator further comprising an eleventh logic unit interconnecting said fourth and fifth output terminals with said input terminal n11, and a 12th logic unit interconnecting said fourth and seventh output terminals with said input terminal n12, said 11th and 12th logic units each including means responsive to the D.C. signals applied to the two output terminals to which the logic unit is connected for generating and applying an electrical signal to the respective input terminal to which the logic unit is connected, said electrical signal being of a duration approximately equal to the duration of the D.C. signals in response to which the electrical signal is generated, the means of said 11th and 12th logic units comprising circuitry responsive to a pair of D.C. signals for generating an output signal and a transistor whose collector is connected to a corresponding one of said input terminals and whose base is connected to said output signal generating circuitry.

Claim 7

The system of claim 4 wherein the meanS of said first through 10th logic unit comprises circuitry responsive to a pair of D.C. signals for generating an output signal and a transistor whose collector is connected to a corresponding one of said input terminals, whose emitter is coupled to a voltage source, and whose base is coupled to the output signal generating circuitry.

Claim 8

The system of claim 5 wherein the means of said first through tenth logic units further comprises a capacitor interconnecting the collector of said transistor to said voltage source, and a resistor interconnecting the base of said transistor to said voltage source.

Claim 9

In a system including a station for generating a plurality of tone signals, and a data set for converting said tone signals to pairs of D.C. signals of duration substantially equal to the duration of the tone signal converted, a data recording unit responsive to D.C. pulses for recording single items of data, and a translator interconnecting said data set and said data recording unit and comprising a plurality of logic means, each responsive to a different pair of D.C. signals from said data set for applying a D.C. pulse to said data recording unit, each of said logic means comprising means responsive to a pair of D.C. signals from said data set for generating an output signal, a first voltage source, a transistor whose collector is coupled to said data recording unit, whose emitter is coupled to said first voltage source, and whose base is coupled to said output signal generating means, a capacitor interconnecting the collector of said transistor to said first voltage source, a second voltage source, and a resistor interconnecting said second voltage source to the collector of said transistor.

Claim 10

In a system including a station for generating a plurality of tone signals, and a data set for converting said tone signals to pairs of D.C. signals of duration substantially equal to the duration of the tone signal converted, a data recording unit responsive to D.C. pulses for recording single items of data, and a translator interconnecting said data set and said data recording unit and comprising a plurality of logic means, each responsive to a different pair of D.C. signals from said data set for applying a D.C. pulse to said data recording unit, each of said logic means comprising means responsive to a pair of D.C. signals from said data set for generating an output signal, a first voltage source, a transistor whose collector is coupled to said data recording unit, whose emitter is coupled to said first voltage source, and whose base is coupled to said output signal generating means, a capacitor interconnecting the collector of said transistor to said first voltage source, a second voltage source, and a resistor interconnecting said second voltage source to the collector of said transistor.

Claim 11

The system of claim 7 wherein each of said logic means further comprises a third voltage source coupled to the base of said transistor and a resistor interconnecting the base of said transistor with said first voltage source.