US3822386A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Noise immune transistor switch
Assignee: Allegro Microsystems LLC
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Filing: 1973-04-04
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Granted: 1974-07-02
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Expires: 1993-04-04
Abstract
Abstract A PNP and an NPN transistor are combined with a few resistors to form a buffer switch that is particularly useful for interfacing transistor logic circuits with remote mechanical switches in a high noise environment. Noise voltages that may be generated in chassis or common ground circuits leading to the logic inputs, must reach a level almost as large as the switching circuit power supply voltage, to cause abnormal switching.
Inventors
- 👤 W Gontowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:24
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
172 words
A switching circuit comprising: two power supply terminals for connection to an external d.c. voltage, one said power supply terminal being the circuit ground reference terminal and the other said power supply terminal being the hot terminal; a first and second bipolar transistor, being of opposite types, the emitter of said first transistor being connected to said hot terminal, the emitter of said second transistor being connected to said ground terminal, and the collectors of said first transistor being connected to the base of said second transistor; a first resistor connected between said ground terminal and said base of said second transistor; a second resistor connected between the base of said first transistor and said hot terminal; a third resistor connected between said base of said first transistor and an input terminal, said transistors and said resistors having been made by a normal silicon integrated circuit process; a remote mechanical switch connected between said input terminal and said ground terminal; and output means being connected to the collector of said second transistor.
Claim 2
Dependent Claim
172 words
A switching circuit comprising: two power supply terminals for connection to an external d.c. voltage, one said power supply terminal being the circuit ground reference terminal and the other said power supply terminal being the hot terminal; a first and second bipolar transistor, being of opposite types, the emitter of said first transistor being connected to said hot terminal, the emitter of said second transistor being connected to said ground terminal, and the collectors of said first transistor being connected to the base of said second transistor; a first resistor connected between said ground terminal and said base of said second transistor; a second resistor connected between the base of said first transistor and said hot terminal; a third resistor connected between said base of said first transistor and an input terminal, said transistors and said resistors having been made by a normal silicon integrated circuit process; a remote mechanical switch connected between said input terminal and said ground terminal; and output means being connected to the collector of said second transistor.
Claim 3
Dependent Claim
13 words
The circuit of claim 1 wherein said first transistor is a PNP type.
Claim 4
Dependent Claim
13 words
The circuit of claim 1 wherein said first transistor is an NPN type.
Claim 5
Dependent Claim
17 words
The circuit of claim 1 having a noise voltage source effectively in series with said mechanical switch.
Claim 6
Dependent Claim
16 words
The circuit of claim 1 wherein said third resistor has a value that is essentially zero.
Claim 7
Dependent Claim
14 words
The circuit of claim 1 wherein said output means consists in an output terminal.
Claim 8
Dependent Claim
81 words
The circuit of claim 1 wherein said output means is comprised of a third transistor of the same type as said second transistor, the emitter of said third transistor being connected to said ground terminal; and a resistor connected between said hot terminal and the base of said third transistor; wherein said connection between said collector of said second transistor and said output means is achieved by connecting said collector of said second transistor to said base of said third transistor.
References Cited (Backward Citations)
US3735153A
Cited
US3684898A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-01 | 1977-12-31 | 1978-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-01 | 1981-12-31 | 1982-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-01 | 1985-12-31 | 1986-07-02 | $7700.00 | Window Closed / Lapsed |