Addition-subtraction device and memory means utilizing stop codes to designate form of stored data

Claim 2

An addition-subtraction device utilizing memory means, comprising: a shift register including a plurality of serially arranged information addresses for storing data items, and including means for storing stop codes interposed between adjacent addresses; an addition-subtraction unit coupled to the input of said shift register, said addition-subtraction unit operating to effect the addition and subtraction of the contents of addresses and said stop code of the shift register, to convert a positive stop code into a complement stop code under control of a borrow signal formed as a result of a subtraction operation and to convert a complement stop code into a positive stop code under control of a carry signal formed as a result of an addition operation; means responsive to at least an output of said shift register for supplying a switching output to switch the operation of said addition-subtraction unit between a decimal operation for input decimal information and another form of operation for said stop codes; and means coupled to at least said means for supplying a switching output for discriminating between said positive stop code and said complement stop code.

Claim 3

The addition-subtraction device utilizing memory means according to claim 1 wherein said stop codes and input data are in the form of binary bit codes and the operation of said addition-subtraction unit is switched between a decimal operation and a hexadecimal operation.

Claim 4

The addition-subtraction device utilizing memory means according to claim 1 including a mark generator coupled to said addition-subtraction unit for writing in said shift register a start code mark and the stop codes through said addition-subtraction unit.

Claim 5

The addition-subtraction device utilizing memory means according to claim 1 wherein said data items have different lengths.

Claim 6

The addition-subtraction device utilizing memory means according to claim 1 wherein said data items have the same length.

Claim 7

The addition-subtraction device utilizing memory means according to claim 1 wherein there are provided a buffer register coupled to said addition-subtraction unit for temporarily storing data items; and means to feed outputs from said shift register into said buffer register; and wherein said means for supplying a switching output includes a counter for detecting the addresses of said shift register, means to set said counter to a predetermined count corresponding to a predetermined address of said shift register in which the input data is to be stored, means responsive to an output of said shift register to enable said counter to count down said predetermined count to a second predetermined count in response to the shifting operation of said shift register, and means responsive to said second predetermined count of said counter to shift the contents of said buffer register so as to write data in said predetermined address of said shift register.

Claim 8

The addition-subtraction device utilizing memory means according to claim 6 wherein an output of said shift register is coupled to an input of said addition-subtraction unit, and which further includes means to write in said buffer register additional input data which is to be added to or subtracted from said input data stored in said shift register so as to apply said additional input data to said addition-subtraction unit together with said input data shifted out from said shift register.

Claim 9

The addition-subtractioN device utilizing memory means according to claim 6 wherein said second predetermined count is zero.

Claim 10

An addition-subtraction device utilizing memory means, comprising: a shift register including a plurality of serially arranged addresses for storing data items, and including means for storing stop codes interposed between adjacent addresses, a buffer register for temporarily storing input data; means to write input data in said buffer register; an addition-subtraction unit coupled to the input of said shift register and to the output of said buffer register for selectively performing addition and subtraction operations on the contents of addresses and said stop code of said shift register and on said input data, said addition-subtraction unit being further coupled to an output of said shift register, a mark generator coupled to said addition-subtraction unit and adapted to selectively generate a start mark F and said stop codes S which are written in said shift register through said addition-subtraction unit; a counter coupled to said shift register for detecting the addresses of said shift register; means to set said counter to a predetermined count corresponding to a predetermined address of said shift register in which input data is to be stored; means to apply the data shifted out from said shift register to said buffer register; a mark detector responsive to the output from said shift register for producing an F detection signal an S detection signal and S'' detection signal corresponding to said start code F, said stop code S and a complement stop code S'', respectively; a first flip-flop circuit which is coupled to said mark detector and to said counter so as to be set by said F detection signal and reset by the output from said counter; means to apply the output from said first flip-flop circuit to said counter to enable said counter to count down from said predetermined count to zero in response to said F detection signal, said S detection signal and said S'' detection signal; a second flip-flop circuit which is coupled to said mark detector and to said counter so as to be set by the zero value output from said counter and reset in response to said S detection signal and said S'' detection signal; means responsive to the output of said second flip-flop circuit to shift the input data in said buffer register; means for applying said shifted input data to said addition-subtraction unit from said buffer register such that said input data is added to or subtracted from said input data stored in said shift register; means including said flip-flop circuit and said counter and being responsive to said stop code for switching the operation of said addition-subtraction unit between a decimal operation and a hexadecimal operation for data to be stored in said shift register, whereby said addition-subtraction unit operates to convert a positive stop code into a complement stop code under the control of a borrow signal formed as a result of a subtraction operation and to convert a complement stop code into a positive stop code under the control of a carrier signal formed as a result of an addition operation; and means coupled to at least said switching means for discriminating between said positive stop code and said complement stop code, both codes being generated as a function of the switching operation of said switching means and being stored in said shift register.

Claim 11

An addition-subtraction device utilizing memory means, comprising: a shift register including a plurality of serially arranged addresses for storing data items, and including means for storing stop codes interposed between adjacent addresses, a buffer register for temporarily storing input data; means to write input data in said buffer register; an addition-subtraction unit coupled to the input of said shift register and to the output of said buffer register for selectively performing addition and subtraction operations on the contents of addresses and said stop code of said shift register and on said input data, said addition-subtraction unit being further coupled to an output of said shift register, a mark generator coupled to said addition-subtraction unit and adapted to selectively generate a start mark F and said stop codes S which are written in said shift register through said addition-subtraction unit; a counter coupled to said shift register for detecting the addresses of said shift register; means to set said counter to a predetermined count corresponding to a predetermined address of said shift register in which input data is to be stored; means to apply the data shifted out from said shift register to said buffer register; a mark detector responsive to the output from said shift register for producing an F detection signal an S detection signal and S'' detection signal corresponding to said start code F, said stop code S and a complement stop code S'', respectively; a first flip-flop circuit which is coupled to said mark detector and to said counter so as to be set by said F detection signal and reset by the output from said counter; means to apply the output from said first flip-flop circuit to said counter to enable said counter to count down from said predetermined count to zero in response to said F detection signal, said S detection signal and said S'' detection signal; a second flip-flop circuit which is coupled to said mark detector and to said counter so as to be set by the zero value output from said counter and reset in response to said S detection signal and said S'' detection signal; means responsive to the output of said second flip-flop circuit to shift the input data in said buffer register; means for applying said shifted input data to said addition-subtraction unit from said buffer register such that said input data is added to or subtracted from said input data stored in said shift register; means including said flip-flop circuit and said counter and being responsive to said stop code for switching the operation of said addition-subtraction unit between a decimal operation and a hexadecimal operation for data to be stored in said shift register, whereby said addition-subtraction unit operates to convert a positive stop code into a complement stop code under the control of a borrow signal formed as a result of a subtraction operation and to convert a complement stop code into a positive stop code under the control of a carrier signal formed as a result of an addition operation; and means coupled to at least said switching means for discriminating between said positive stop code and said complement stop code, both codes being generated as a function of the switching operation of said switching means and being stored in said shift register.

Claim 12

An addition-subtraction device according to claim 9 wherein said last mentioned means is supplied with said S'' detection code from said mark detector and the output from said counter.