Switching transistor with memory
Abstract
Abstract A SWITCHING TRANSISTOR WITH MEMORY IS PROVIDED IN WHICH IS SELECTED JUNCTION (PREFERABLY THE BASE-EMITTER JUNCTION) IS FABRICATED TO HAVE A HIGH INJECTION EFFICIENCY AND MULTIPLE ACCEPTOR OR MULTIPLE DONOR TRAPPING CENTERS DISTRIBUTED IN AND AROUND THE DEPLETION REGION OF THE JUNCTION. THE TRAPPING CENTERS ARE CHOSEN TO BE OF A TYPE FOR FIELD-INDUCED TRAPING DOMINANT CARRIERS TRANSPORTED ACROSS THE SELECTED JUNCTION WHEN FORWARD BIASED. TO SWITCH THE TRANSISTOR FROM ONE I-V CHARACTERISTIC TO A LOWER I-V CHARACTERISTIC, THE SELECTED JUNCTION IS BIASED IN A FORWARD DIRECTION TO A PREDETERMINED THRESHOLD LEVEL FOR FIELD-INDUCED TRAPPING OF SAID CARRIERS BY THE DISTRIBUTED TRAPPING CENTERS, THEREBY CREATING A STABLE AND STATIONARY SPACE CHARGE DOMAIN IN THE CURRENT PATH OF THE SELECTED JUNCTION. THE TRANSISTOR IS RESET BY REVERSE BIASING THE SELECTED JUNCTION TO A LEVEL WHERE THE SPACE DOMAIN IS ANNIHILATED.
Inventors
- 👤 D Heald
- 👤 Kennedy J Holm
Bibliographic Details
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