Temporary storage apparatus

Claim 1

Apparatus for temporarily storing a plurality of N X M bits which are received in M groups of bits in series, each group of the series consisting of N bits in parallel, said apparatus comprising a gorup of N input terminals adapted to receive N bits of input data in parallel; a plurality of N X M latching means arranged in an electrical matrix of N rows by M columns; each latching means having an input connection, an output connection, and a control connection, each latching means being operable to transfer the bit at its input connection to its output connection while a first control signal is present at its control connection, and being operable to store the bit present at its input connection when the signal at the control connection changes from the first control signal to a second control signal until the signal at the control connection changes from the second control signal to the first control signal; the input connection of each latching means being connected to the output connection of the latching means in the preceding column of the same row, the input connection of each latching means in the first column being connected to the corresponding input terminal; and control means having a clock connection, a reset connection, and M output connections arranged in succession, each output connection of the control means being connected to all the control connections of the latching means of the corresponding column, said control means being operable to produce said first control signal at all of said output connections in response to a reset signal at said reset connection and being operable to cause the signal at each output connection in reverse succession from last to first to change from the first control signal to the second control signal in response to clock pulses at the clock connection so that after M clock pulses second control signals are produced at all the output connections; whereby, subsequent to a reset signal applied to said reset connection, when a group of N bits in parallel is applied to said N input terminals and a clock pulse is applied to the clock connection of said control means during the time the group of bits is being applied to the input terminals, bits of input data are passed along the N rows of latching means and stored in the latching means of the column of highest order in the succession not having bits of data already stored therein; and after a series of M groups of N bits are applied to the input terminals and M clock pulses have been applied to the clock connection, N X M bits are stored in the N X M latching means.