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US3821716A
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Method and apparatus for recovering data in an nrzi recording system
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1973-03-05
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Granted: 1974-06-28
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Expires: 1993-03-05
Abstract
Abstract Apparatus for detecting missing pulses in recovered NRZI encoded data. Positive and negative read signals are separated and applied to different error detecting circuits. Each error detecting circuit has a three stage, serial-transfer, shift register. The second stage output is connected to one circuit output terminal. The first and third stage outputs are applied to a conventional AND gate. The AND gate transmits an output pulse to the second circuit output terminal whenever the first and third stages contain logical ''''1''''s since the NRZI code dictates that an intermediate pulse of the opposite polarity must be missing. The circuit output terminals from both error detecting circuits are connected to the input of an OR gate.
Inventors
- 👤 P Ghajar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:25
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
165 words
An error detecting and correcting apparatus for use in recovering NRZI encoded data from a data storage device comprising: a. pulse generating means for receiving an analog read signal and for producing a first stream of pulses representing positive read signals and a second stream of pulses representing negative read signals; b. thresholding means connected to said pulse generating means and the analog read signal source for passing only pulses having an amplitude exceeding a predetermined threshold amplitude; c. a first error detecting circuit for receiving the first pulse stream and a second error detecting circuit for receiving the second pulse stream, each of said error detecting circuits including: 1. means for storing successive triplets of signals received from said thresholding means, and 2. means for logically ANDing the first and third stored signals; and d. means for logically ORing the output of said AND means in both of said error detecting circuits with the second stored signal in both of said error detecting circuits.
Claim 2
Dependent Claim
165 words
An error detecting and correcting apparatus for use in recovering NRZI encoded data from a data storage device comprising: a. pulse generating means for receiving an analog read signal and for producing a first stream of pulses representing positive read signals and a second stream of pulses representing negative read signals; b. thresholding means connected to said pulse generating means and the analog read signal source for passing only pulses having an amplitude exceeding a predetermined threshold amplitude; c. a first error detecting circuit for receiving the first pulse stream and a second error detecting circuit for receiving the second pulse stream, each of said error detecting circuits including: 1. means for storing successive triplets of signals received from said thresholding means, and 2. means for logically ANDing the first and third stored signals; and d. means for logically ORing the output of said AND means in both of said error detecting circuits with the second stored signal in both of said error detecting circuits.
Claim 3
Dependent Claim
22 words
clocking means for serially shifting the pulse stream through said register with a frequency corresponding to the analog signal read frequency, and
Claim 4
Dependent Claim
22 words
clocking means for serially shifting the pulse stream through said register with a frequency corresponding to the analog signal read frequency, and
Claim 5
Dependent Claim
112 words
An error detecting and correcting apparatus for use in recovering NRZI encoded data read from a data storage device comprising: a. pulse generating means for receiving an analog read signal and for producing a first stream of pulses representing positive read signals and a separate second stream of pulses representing negative read signals; b. thresholding means connected to said pulse generating means and the analog read signal source for passing only pulses which have an amplitude exceeding a predetermined threshold amplitude; c. a first error detecting circuit for receiving the first pulse stream and a second error detecting circuit for receiving the second pulse stream, each of said error detecting circuits including:
Claim 6
Dependent Claim
112 words
An error detecting and correcting apparatus for use in recovering NRZI encoded data read from a data storage device comprising: a. pulse generating means for receiving an analog read signal and for producing a first stream of pulses representing positive read signals and a separate second stream of pulses representing negative read signals; b. thresholding means connected to said pulse generating means and the analog read signal source for passing only pulses which have an amplitude exceeding a predetermined threshold amplitude; c. a first error detecting circuit for receiving the first pulse stream and a second error detecting circuit for receiving the second pulse stream, each of said error detecting circuits including:
Claim 7
Dependent Claim
41 words
means for logically ANDing the first and third stored signals; and d. means for logically ORing the output of said AND means in both of said error detecting circuits with the second stored signal in both of said error detecting circuits.
Claim 8
Dependent Claim
41 words
means for logically ANDing the first and third stored signals; and d. means for logically ORing the output of said AND means in both of said error detecting circuits with the second stored signal in both of said error detecting circuits.
Claim 9
Dependent Claim
68 words
an AND gate having inputs connected to the outputs of the first and third stages of said register to generate an error correction output signal when pulses are concurrently stored in those stages; and d. an OR gate having inputs from the output side of the AND gate and output side of the second stage of said register in both of said first and second error detecting circuits.
Claim 10
Dependent Claim
68 words
an AND gate having inputs connected to the outputs of the first and third stages of said register to generate an error correction output signal when pulses are concurrently stored in those stages; and d. an OR gate having inputs from the output side of the AND gate and output side of the second stage of said register in both of said first and second error detecting circuits.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-27 | 1977-12-27 | 1978-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-27 | 1981-12-27 | 1982-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-27 | 1985-12-27 | 1986-06-28 | $7700.00 | Window Closed / Lapsed |