Electronic control unit for the linking of symmetrical closed chains of words in a random access memory

Claim 1

In combination with a conventional random-access memory having a read-write data register, an address register, and command wires therefor, an electronic control device comprising: a control register circuit means (20-1) of conventional type characterized by a specific register (k) having different possible states, two externally modifiable registers (R1 and R2) of conventional flip-flop type, incrementing means (5-4) connected to oNe of said registers (R2) for incrementing, by one, the contents of said one of said registers (R2), said control register circuit means including a plurality of gates and logical circuit means interconnected with said specific register, said address register and said externally modifiable registers for transferring and comparing binary information between said address, read-write and externally modifiable registers and for controlling accesses to the address register of the random access memory, to two defined and specialized segments of the memory, to command wires of the random access memory read-write data register, and to command wires of the random access memory, each state of the specific register (k) in the control register circuit means corresponding to a determined one phase of several possible phases of the gates and logical circuit means in the control device and the sequence of said phases being triggered by an external initialization command means (5-3-1, 5-3-2), said gates and logical circuit means including: a conventional combination of logic circuit means (5-2) connected to determine the content of said specific register (k) therein according to said states, and further means (5-1a, 5-1b) to cause four predetermined ones of said phases (phases 1-4) to successively act in turn to form one cycle of initialization (IN) corresponding to the chaining of a word of the random access memory and which four predetermined phases are caused by said further means to act collectively by incrementing, comparing and transferring binary information between specified ones of said address, read-write and externally modifiable registers and to emit appropriate command signals along said command wires to the random access memory for each of the words being accessed in the random access memory thereby initially linking all such words together in a reserve chain, said further means for causing said cycle of initialization including: means to produce a corresponding cycle for writing the address (from RI) of an immediate neighbor word in a negative or backward direction, in a first segment of said word corresponding to a first segment LI of the read-write data register means for writing the address (from R2) of the immediate neighbor word in a positive or forward direction in another second segment of the said word corresponding to a second segment L2 of the read-write data register by appropriate commands to the random access memory wherein this writing is made for all the words being accessed by incrementing by one unit the contents of the two segments L1 and L2 of the readwrite register cited above at each cycle, and means for disrupting the cyclic initialization in response to an eventual response of a test of comparison made at each cycle with the address of the word at the beginning of the command, (000 . . . for example), so that all words of the random access memory being accessed are caused to be elements of an initial closed symmetrical reserve chain, the two segments of all of the words of the random access memory corresponding to L1 and L2 being backward and forward pointers respectively where other segments or parts of these words are utilized for the storage and processing of external information.