Patent US3821634A successfully refreshed from Google Patents.
US3821634A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Externally regulated power phase control circuit
Assignee: Tony Construction Inc
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Filing: 1972-10-02
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Granted: 1974-06-28
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Expires: 1992-10-02
Abstract
Abstract An electrical circuit is disclosed whereby power phase control may be uniquely achieved in correlation with any of numerous external control sources. A timing circuit is utilized in conjunction with a diac-triac power control circuit to achieve the desired regulation. An external programmed signal source provides predetermined signals to achieve control of the timing circuit. Consequently, the external programmed signal source directly affects the degree of power regulation of the diac-triac control circuit.
Inventors
- 👤 D Sabolic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:57
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/12; G05F1/40; G05F1/44; G05F1/445
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
256 words
A circuit for regulating the electrical power from an AC line voltage to a load, comprising: a step-up transformer connected to the AC line amplifying the line voltage and thereby providing an output wave form wherein the individual cycles have faster rise and fall times than those of the line voltage; a full wave rectifier receiving and rectifying the output from the transformer and passing a full rectified signal to a clamping zener diode and thence to a capacitor and resistor network wherein the clamped full wave rectified signal from the zener diode is smoothed into a stable DC level; a timing circuit interconnected between the zener diode and the capacitor and resistor network including a resistor series connected to a timing capacitor and a transistor in shunt with the timing capacitor, the transistor controlling the rate of charge of the timing capacitor according to its degree of conductivity; a diac-triac power control circuit connected to the timing circuit and the load for regulating the power to the load in accordance with the rate of charge of the timing capacitor; a diode interconnected between the full wave rectifier and the timing capacitor and providing a discharge path for the timing capacitor at the end of each half cycle of the line voltage; a program signal source coupled to the transistor and applying a dynamically changing pulse thereto for controlling the conductivity of the transistor; and variable DC biasing means interconnected between the transistor and the capacitor and resistor network to control the conductivity of the transistor.
Claim 2
Dependent Claim
256 words
A circuit for regulating the electrical power from an AC line voltage to a load, comprising: a step-up transformer connected to the AC line amplifying the line voltage and thereby providing an output wave form wherein the individual cycles have faster rise and fall times than those of the line voltage; a full wave rectifier receiving and rectifying the output from the transformer and passing a full rectified signal to a clamping zener diode and thence to a capacitor and resistor network wherein the clamped full wave rectified signal from the zener diode is smoothed into a stable DC level; a timing circuit interconnected between the zener diode and the capacitor and resistor network including a resistor series connected to a timing capacitor and a transistor in shunt with the timing capacitor, the transistor controlling the rate of charge of the timing capacitor according to its degree of conductivity; a diac-triac power control circuit connected to the timing circuit and the load for regulating the power to the load in accordance with the rate of charge of the timing capacitor; a diode interconnected between the full wave rectifier and the timing capacitor and providing a discharge path for the timing capacitor at the end of each half cycle of the line voltage; a program signal source coupled to the transistor and applying a dynamically changing pulse thereto for controlling the conductivity of the transistor; and variable DC biasing means interconnected between the transistor and the capacitor and resistor network to control the conductivity of the transistor.
Claim 3
Dependent Claim
272 words
A circuit for regulating the electrical power from an AC line voltage to a load, comprising: a step-up transformer connected to the AC line amplifying the line voltage and thereby providing an output wave form wherein the individual cycles have faster rise and fall times than those of the line voltage; a full wave rectifier receiving and rectifying the output from the transformer and passing a full rectified signal to a clamping zener diode and thence to a capacitor and resistor network wherein the clamped full wave rectified signal from the zener diode is smoothed into a stable DC level; a timing circuit interconnected between the zener diode and the capacitor and resistor network and including a resistor series connected to a timing capacitor and a first transistor in shunt with the timing capacitor, the first transistor controlling the rate of charge of the timing capacitor according to its degree of conductivity; a diac-triac power cOntrol circuit connected to the timing circuit and the load for regulating the power to the load in accordance with the rate of charge of the timing capacitor; a second transistor in shunt with the timing capacitor and operatively connected to and receiving a full wave rectified signal from the rectifier and providing a discharge path for the timing capacitor at the end of each half cycle of the line voltage and wherein the first transistor is rendered temperature insensitive by means of a voltage divider network connected to the base thereof; and variable DC biasing means interconnected between the first transistor and the capacitor and resistor network to further control the conductivity of the first transistor.
Claim 4
Dependent Claim
272 words
A circuit for regulating the electrical power from an AC line voltage to a load, comprising: a step-up transformer connected to the AC line amplifying the line voltage and thereby providing an output wave form wherein the individual cycles have faster rise and fall times than those of the line voltage; a full wave rectifier receiving and rectifying the output from the transformer and passing a full rectified signal to a clamping zener diode and thence to a capacitor and resistor network wherein the clamped full wave rectified signal from the zener diode is smoothed into a stable DC level; a timing circuit interconnected between the zener diode and the capacitor and resistor network and including a resistor series connected to a timing capacitor and a first transistor in shunt with the timing capacitor, the first transistor controlling the rate of charge of the timing capacitor according to its degree of conductivity; a diac-triac power cOntrol circuit connected to the timing circuit and the load for regulating the power to the load in accordance with the rate of charge of the timing capacitor; a second transistor in shunt with the timing capacitor and operatively connected to and receiving a full wave rectified signal from the rectifier and providing a discharge path for the timing capacitor at the end of each half cycle of the line voltage and wherein the first transistor is rendered temperature insensitive by means of a voltage divider network connected to the base thereof; and variable DC biasing means interconnected between the first transistor and the capacitor and resistor network to further control the conductivity of the first transistor.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-27 | 1977-12-27 | 1978-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-27 | 1981-12-27 | 1982-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-27 | 1985-12-27 | 1986-06-28 | $7700.00 | Window Closed / Lapsed |