Patent US3820153A successfully refreshed from Google Patents.
US3820153A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Plurality of semiconductor elements mounted on common base
Assignee: Zyrotron Ind Inc
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Filing: 1972-08-28
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Granted: 1974-06-25
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Expires: 1992-08-28
Abstract
Abstract The array comprising a metallic base having a high thermal conductivity which receives a first layer of material having a high thermal conductivity and low electrical conductivity. A plurality of semiconductor elements are mounted on the first layer of material in juxtaposition to each other and a second layer of material having the same characteristics as the first layer of material covers the first layer of material and the semiconductor elements. A method of fabricating the array of semiconductor elements also is disclosed.
Inventors
- 👤 F Quinn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:19
CPC Classifications
H; H10; H10W; H10W40/00; H10W40/70; H10W90/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
101 words
An array of individual semiconductor elements comprising a single metallic base having a high thermal conductivity, a first layer of material on said base having a low electrical conductivity and a high thermal conductivity, a plurality of individual longitudinally spaced semiconductor elements on said first layer of material, each of said plurality of semiconductor elements have at least two laterally spaced terminals extending upwardly from said base, and a second layer of material contiguous with said first layer and having a low electrical conductivity and a high thermal conductivity covering said first layer of material and said plurality of semiconductor elements.
Claim 2
Dependent Claim
101 words
An array of individual semiconductor elements comprising a single metallic base having a high thermal conductivity, a first layer of material on said base having a low electrical conductivity and a high thermal conductivity, a plurality of individual longitudinally spaced semiconductor elements on said first layer of material, each of said plurality of semiconductor elements have at least two laterally spaced terminals extending upwardly from said base, and a second layer of material contiguous with said first layer and having a low electrical conductivity and a high thermal conductivity covering said first layer of material and said plurality of semiconductor elements.
Claim 3
Dependent Claim
20 words
An array of semiconductor elements as in claim 1, in which said plurality of semiconductor elements each comprise a diode.
Claim 4
Dependent Claim
59 words
An array of semiconductor elements as in claim 2, in which said base includes a bottom wall, and opposed side walls having inner surfaces which taper downwardly and outwardly to define a dovetail groove, said opposed walls extending above said first and second layers of material whereby said first and second layers of material are retained within said groove.
Claim 5
Dependent Claim
68 words
An array of semiconductor elements as in claim 3, (in which each one of said plurality of semiconductor elements comprises a pair of terminals,) a semiconductor chip having a lead at one end and a base at the other end, means for electrically connecting said base end to one of said (pair of) two terminals, and means for connecting said lead end to the other of said terminals.
Claim 6
Dependent Claim
120 words
An array of semiconductor elements as in claim 4, in which each terminal of said pair of terminals is L-shaped and has a horizontal and a vertical leg, said lead being connected to the horizontal leg of one of said terminals and said base being connected to the horizontal leg of the other of said terminals, said horizontal legs of said pair of terminals being mounted on said first layer of material in spaced relationship to each other with said vertical legs in opposing relationship, one of said vertical legs having a different shape than the other of said vertical legs of said pair of terminals to designate the terminal to which the base of said semiconductor element is connected.
Claim 7
Dependent Claim
22 words
An array of semiconductor elements as in claim 5, in which said first and second layers of material are identical in composition.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-24 | 1977-12-24 | 1978-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-24 | 1981-12-24 | 1982-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-24 | 1985-12-24 | 1986-06-25 | $7700.00 | Window Closed / Lapsed |