Patent US3820084A successfully refreshed from Google Patents.
US3820084A
Expired / Lapsed
US
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Computer processor register and bus arrangement
Assignee: AG Communication Systems Corp
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Filing: 1973-03-01
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Granted: 1974-06-25
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Expires: 1993-03-01
Abstract
Abstract The computer processor comprises a plurality of registers and an arithmetic logic unit along with interfaces with other units of a data processing system connected as sources and sinks to one data bus and one address bus. Each source for a bus has leads from the output of a register or a set of interface leads connected to inputs of AND function gates with the gates for a selected source enabled by a control signal, and the outputs of the respective bits of the AND gates of the several sources are connected to OR function gates, the outputs of which comprise the bus. A register or set of interface leads acting as a sink has the bus connected to the inputs of AND function gates whose outputs are connected to the inputs of the register or interface leads, and the gates for a sink are enabled by a sink select signal. Each of the buses also has its leads connected back as source leads to AND function gates which are enabled by a LATCH signal, thereby effectively making the bus act as a register. For certain instructions of the order set, either or both buses may be latched during the processing to retain information while the source register is used for other purposes.
Inventors
- 👤 L Jones
- 👤 P Keehn
- 👤 P Zelinski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:10
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
434 words
A computer central processor in a digital processing system which comprises said processor, a memory, and other subsystems; wherein said processor comprises a plurality of registers, each comprising a plurality of bistable devices for alternatively storing ''''ones'''' and ''''zeros,'''' said registers including an arithmetic input register, an arithmetic output register, an accumulator register, and an instruction register, a data bus comprising a plurality of conductors, source gating means coupling a first set of said registers, data lines from other subsystems, and a set of data conductors from the memory to the data bus, sink gating means coupling the data bus to a second set of said registers, including the arithmetic output register and the accumulator register, the data bus being also coupled to the main memory and to other subsystems, certain ones of said registers being included in both said first set and said second set, an arithmetic logic unit, with arithmetic input gating means from the data bus and the arithmetic input register to the arithmetic logic unit, and arithmetic output gating means from the arithmetic logic unit to the arithmetic output register and the accumulator register, control logic means connected to supply control signals to selectively enable said gating means to transfer data to and from the data bus and into and out of the arithmetic logic unit, and to selectively enable said gating means to transfer instructions from the instruction register to said control logic means, timing means responsive to a source of clock pulses to supply a sequence of timing interval signals on a plurality of timing leads coupled to the control logic means; wherein said source gating means includes a set comprising one data bus latching gate for each data bus conductor, each having an input from its data bus conductor and an output to the same conductor, and a latch data bus lead from said control logic means to all of the data bus latching gates so that responsive to a latch data bus enable signal condition on the latch data bus lead all ''''ones'''' on data bus conductors are latched; means in said control logic means responsive to given instructions transferred from the instruction register to enable the source gating means to the data conductors from the memory to gate data from memory onto the data bus, to supply the latch data bus enable signal to independently retain the data on the data bus after removing said enable of the source gating means for the data conductors from the memory, so that the memory may be released while retaining the data for processing during subsequent timing intervals.
Claim 2
Dependent Claim
434 words
A computer central processor in a digital processing system which comprises said processor, a memory, and other subsystems; wherein said processor comprises a plurality of registers, each comprising a plurality of bistable devices for alternatively storing ''''ones'''' and ''''zeros,'''' said registers including an arithmetic input register, an arithmetic output register, an accumulator register, and an instruction register, a data bus comprising a plurality of conductors, source gating means coupling a first set of said registers, data lines from other subsystems, and a set of data conductors from the memory to the data bus, sink gating means coupling the data bus to a second set of said registers, including the arithmetic output register and the accumulator register, the data bus being also coupled to the main memory and to other subsystems, certain ones of said registers being included in both said first set and said second set, an arithmetic logic unit, with arithmetic input gating means from the data bus and the arithmetic input register to the arithmetic logic unit, and arithmetic output gating means from the arithmetic logic unit to the arithmetic output register and the accumulator register, control logic means connected to supply control signals to selectively enable said gating means to transfer data to and from the data bus and into and out of the arithmetic logic unit, and to selectively enable said gating means to transfer instructions from the instruction register to said control logic means, timing means responsive to a source of clock pulses to supply a sequence of timing interval signals on a plurality of timing leads coupled to the control logic means; wherein said source gating means includes a set comprising one data bus latching gate for each data bus conductor, each having an input from its data bus conductor and an output to the same conductor, and a latch data bus lead from said control logic means to all of the data bus latching gates so that responsive to a latch data bus enable signal condition on the latch data bus lead all ''''ones'''' on data bus conductors are latched; means in said control logic means responsive to given instructions transferred from the instruction register to enable the source gating means to the data conductors from the memory to gate data from memory onto the data bus, to supply the latch data bus enable signal to independently retain the data on the data bus after removing said enable of the source gating means for the data conductors from the memory, so that the memory may be released while retaining the data for processing during subsequent timing intervals.
Claim 3
Dependent Claim
218 words
A computer central processor according to claim 1, further including an address bus comprising a plurality of address conductors, wherein one of said registers in a program counter, address source gating means coupling the program counter and the arithmetic output register to the address bus, means coupling the address bus to the memory, wherein said address source gating means includes a set comprising one address bus latching gate for each address bus conductor, each having an input from its address bus conductor and an output to the same conductor, and an latch address bus lead to all of the address latching gates so that responsive to a latch address bus enable signal condition on the latch address bus lead all ''''ones'''' on the address bus are latched; means in said control logic means responsive to certain instructions transferred from the instruction register to enable the address source gating means from the arithmetic output register to gate address information from the arithmetic output register to the address bus, to supply the latch address bus enable signal to independently retain the address information on the address bus after removing said enable of the address source gating means, so that the arithmetic output register may be used for other functions while retaining the address information for processing during subsequent timing intervals.
Claim 4
Dependent Claim
189 words
A computer central processor according to claim 2, wherein an ''''add to memory'''' instruction is both one of said given instructions for data bus latching and one of said certain instructions for address bus latching, wherein there is included means to load the effective address for data into the arithmetic output register and then to gate it to the address bus, means to use this address from the address bus to read data from that address, and to latch the address bus, means for gating data from the accumulator register via the data bus to the arithmetic input register; means for gating data from memory to the data bus which is then latched; data means for gating data from the arithmetic input register and the data bus in the arithmetic logic unit and loading the result into the arithmetic output register; means for supplying data via the data bus from the arithmetic output register and to supply the address from the address bus to the memory Along with a write enable signal; all of said operations being controlled by signals from said control logic means and said timing means.
Claim 5
Dependent Claim
64 words
A computer central processor according to claim 3, wherein there are instructions ''''add one to memory'''' and ''''subtract one from memory'''' which are also both given instructions for data bus latching and certain instructions for address bus latching; and means to execute these instructions which include the same means for data bus and address bus latching as used with the ''''add to memory'''' instruction.
Claim 6
Dependent Claim
31 words
A computer central processor according to claim 4, wherein said latch address bus lead is the output of a bistable device having set and reset inputs from the control logic means.
Claim 7
Dependent Claim
380 words
A computer central processor in a digital processing system which comprises said processor, a memory, and other subsystems; wherein said processor comprises a plurality of registers, each comprising a plurality of bistable devices for alternatively storing ''''ones'''' and ''''zeros,'''' said registers including an arithmetic input register, an arithmetic output register, an accumulator register, an instruction register, and a program counter; an arithmetic logic unit, with arithmetic input gating means from the arithmetic input register to the arithmetic logic unit, and arithmetic output gating means from the arithmetic logic unit to the arithmetic output register and the accumulator register, an address bus comprising a plurality of address conductors; address source gating means coupling the program counter and the arithmetic output register to the address bus; means coupling the address bus to the memory; control logic means to supply control signals to selectively enable said gating means to transfer information to the address bus and into and out of the arithmetic logic unit, and to selectively enable said gating means to transfer instructions from the instruction register to said control logic means, timing means responsive to a source of clock pulses to supply a sequence of timing interval signals on a plurality of timing leads coupled to the control logic means; wherein said address source gating means includes a set comprising one address bus latching gate for each address bus conductor, each having an input from its address bus conductor and an output to the same conductor, and an latch address bus lead from said control logic means to all of the address bus latching gates so that responsive to a latch address bus enable signal condition on the latch address bus lead all ''''ones'''' on the address bus are latched; means in said control logic means responsive to certain instructions transferred from the instruction register to enable the address source gating means from the arithmetic output register to gate address information from the arithmetic output register to the address bus, to supply the latch address bus enable signal to independently retain the address information on the address bus after removing said enable of the address source gating means, so that the arithmetic output register may be used for other functions while retaining the address information for processing during subsequent timing intervals.
Claim 8
Dependent Claim
380 words
A computer central processor in a digital processing system which comprises said processor, a memory, and other subsystems; wherein said processor comprises a plurality of registers, each comprising a plurality of bistable devices for alternatively storing ''''ones'''' and ''''zeros,'''' said registers including an arithmetic input register, an arithmetic output register, an accumulator register, an instruction register, and a program counter; an arithmetic logic unit, with arithmetic input gating means from the arithmetic input register to the arithmetic logic unit, and arithmetic output gating means from the arithmetic logic unit to the arithmetic output register and the accumulator register, an address bus comprising a plurality of address conductors; address source gating means coupling the program counter and the arithmetic output register to the address bus; means coupling the address bus to the memory; control logic means to supply control signals to selectively enable said gating means to transfer information to the address bus and into and out of the arithmetic logic unit, and to selectively enable said gating means to transfer instructions from the instruction register to said control logic means, timing means responsive to a source of clock pulses to supply a sequence of timing interval signals on a plurality of timing leads coupled to the control logic means; wherein said address source gating means includes a set comprising one address bus latching gate for each address bus conductor, each having an input from its address bus conductor and an output to the same conductor, and an latch address bus lead from said control logic means to all of the address bus latching gates so that responsive to a latch address bus enable signal condition on the latch address bus lead all ''''ones'''' on the address bus are latched; means in said control logic means responsive to certain instructions transferred from the instruction register to enable the address source gating means from the arithmetic output register to gate address information from the arithmetic output register to the address bus, to supply the latch address bus enable signal to independently retain the address information on the address bus after removing said enable of the address source gating means, so that the arithmetic output register may be used for other functions while retaining the address information for processing during subsequent timing intervals.
Claim 9
Dependent Claim
31 words
A computer central processor according to claim 6, wherein said latch address bus lead is the output of a bistable device having set and reset inputs from the control logic means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-24 | 1977-12-24 | 1978-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-24 | 1981-12-24 | 1982-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-24 | 1985-12-24 | 1986-06-25 | $7700.00 | Window Closed / Lapsed |