Patent US3820032A successfully refreshed from Google Patents.
US3820032A
Expired / Lapsed
US
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Digital circuit for use as a frequency-to-dc transducer
Assignee: International Business Machines Corp
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Filing: 1972-06-30
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Granted: 1974-06-25
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Expires: 1992-06-30
Abstract
Abstract A digital system for converting the repetition rate (frequency) of an input signal into a proportional analog output signal, either in a single-ended or in a differential mode, is described. Basically, the system operates by generating exactly one square pulse for each recurrence of the input signal waveform. The duration of the output pulse is controlled by the repetition rate (frequency) of a timing source external to the frequency-to-DC converter, and the output amplitude is controlled by an external reference source. Thus, duration and amplitude of the output waveform are substantially independent of voltage and frequency fluctuations of the input signals, and of drifts in the converter circuit. Moreover, in the differential arrangement, drifts of the common external frequency and voltage references tend to cancel.
Inventors
- 👤 H Schlaeppi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:03
CPC Classifications
H; H03; H03D; H03D3/00; H03D3/02; H03D3/04; G; G01; G01P; G01P3/00; G01P3/42; G01P3/56; G01P3/60; G01R; G01R23/00; G01R23/02; G01R23/06; H03K; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
198 words
A frequency-to-DC square wave converter system comprising an input signal having a discrete frequency in the form of a series of signal pulses, a first circuit responsive to said input signal for producing a finite duration output signal in response to each of said signal pulses, a pulse generator circuit for producing a series of equally spaced timing pulses, and a second circuit responsive to each said finite duration output signal from said first circuit and a concurrent pulse from said pulse generator for initiating an oUtput pulse and further responsive to a subsequent timing pulse from said pulse generator occurring after the duration of said output signal from said first circuit for terminating said output pulse, said second circuit including an And circuit responsive to said output from said first circuit and to said timing pulses from said pulse generator to produce an output gating pulse, and a flip-flop circuit responsive to said output pulse from said gating pulse from said And circuit for terminating said output pulse, and a delay circuit connected between the output of said And circuit and said first circuit for resetting said first circuit to terminate said finite duration output signal therefrom.
Claim 2
Dependent Claim
198 words
A frequency-to-DC square wave converter system comprising an input signal having a discrete frequency in the form of a series of signal pulses, a first circuit responsive to said input signal for producing a finite duration output signal in response to each of said signal pulses, a pulse generator circuit for producing a series of equally spaced timing pulses, and a second circuit responsive to each said finite duration output signal from said first circuit and a concurrent pulse from said pulse generator for initiating an oUtput pulse and further responsive to a subsequent timing pulse from said pulse generator occurring after the duration of said output signal from said first circuit for terminating said output pulse, said second circuit including an And circuit responsive to said output from said first circuit and to said timing pulses from said pulse generator to produce an output gating pulse, and a flip-flop circuit responsive to said output pulse from said gating pulse from said And circuit for terminating said output pulse, and a delay circuit connected between the output of said And circuit and said first circuit for resetting said first circuit to terminate said finite duration output signal therefrom.
Claim 3
Dependent Claim
236 words
A frequency-to-square wave converter system comprising an input signal having a discrete frequency in the form of a series of signal pulses, a first circuit responsive to said input signal for producing a finite duration output signal in response to each of said signal pulses, a pulse generator circuit for producing a series of equally spaced timing pulses, and a second circuit responsive to each said finite duration output signal from said first circuit and a concurrent pulse from said pulse generator for initiating an output pulse and further responsive to a subsequent timing pulse from said pulse generator occurring after the duration of said output signal from said first circuit for terminating said output pulse, said first circuit including a first flip-flop circuit responsive to each of said series of signal pulses of said input signal for producing a finite duration output signal, an And circuit connected to said first flip-flop circuit and said pulse generator and responsive to both a finite duration pulse from said first flip-flop and a timing pulse from said pulse generator for producing an output gating pulse, a second flip-flop circuit connected to the output gating pulse of said And circuit for initiating an output pulse, said second flip-flop being reset in response to a subsequent timing pulse from said pulse generator occurring in the absence of an output gating pulse from said And circuit for terminating said output pulse.
Claim 4
Dependent Claim
236 words
A frequency-to-square wave converter system comprising an input signal having a discrete frequency in the form of a series of signal pulses, a first circuit responsive to said input signal for producing a finite duration output signal in response to each of said signal pulses, a pulse generator circuit for producing a series of equally spaced timing pulses, and a second circuit responsive to each said finite duration output signal from said first circuit and a concurrent pulse from said pulse generator for initiating an output pulse and further responsive to a subsequent timing pulse from said pulse generator occurring after the duration of said output signal from said first circuit for terminating said output pulse, said first circuit including a first flip-flop circuit responsive to each of said series of signal pulses of said input signal for producing a finite duration output signal, an And circuit connected to said first flip-flop circuit and said pulse generator and responsive to both a finite duration pulse from said first flip-flop and a timing pulse from said pulse generator for producing an output gating pulse, a second flip-flop circuit connected to the output gating pulse of said And circuit for initiating an output pulse, said second flip-flop being reset in response to a subsequent timing pulse from said pulse generator occurring in the absence of an output gating pulse from said And circuit for terminating said output pulse.
Claim 5
Dependent Claim
54 words
A frequency-to-fixed-length square wave converter system according to claim 2 further including a delay circuit connected between the output of said And circuit and said first flip-flop circuit to provide a reset pulse to said first flip-flop circuit at a finite time after the occurrence of said output gating pulse from said And circuit.
Claim 6
Dependent Claim
277 words
A frequency-to-DC converter system adapted as a digital tachometer including an input signal having a discrete frequency in the form of a series of signal pulses a first circuit responsive to said input signal for producing a finite duration output signal in response to each of said signal pulses, a pulse generator circuit for producing a series of equally spaced timing pulses; a second circuit responsive to each said finite duration output signal from said first circuit and a concurrent pulse from said pulse generator for initiating an output pulse and further responsive to a subsequent timing pulse from said pulse generator occurring after the duration of said output signal from said first circuit for terminating said output pulse, a first set of said first and said second circuits and a second set of said first and said second circuits connected to a single common clock generator, the input signals of said first set and said second set of circuits having different frequencies, a third circuit connected to the output of said first set of said first and said second circuits, a fourth circuit connected to the output of said second set of said first and said second circuits, a source of reference voltage connected to said third and fourth circuits, a first low pass filter connected to the output of said third circuit, a second low pass filter connected to the output of said fourth circuit, and a differential amplifier connected to the output of said first and second low pass filters for providing a frequency error signal proportional to the difference in frequency between said input signals to said first and second pairs of circuits.
Claim 7
Dependent Claim
277 words
A frequency-to-DC converter system adapted as a digital tachometer including an input signal having a discrete frequency in the form of a series of signal pulses a first circuit responsive to said input signal for producing a finite duration output signal in response to each of said signal pulses, a pulse generator circuit for producing a series of equally spaced timing pulses; a second circuit responsive to each said finite duration output signal from said first circuit and a concurrent pulse from said pulse generator for initiating an output pulse and further responsive to a subsequent timing pulse from said pulse generator occurring after the duration of said output signal from said first circuit for terminating said output pulse, a first set of said first and said second circuits and a second set of said first and said second circuits connected to a single common clock generator, the input signals of said first set and said second set of circuits having different frequencies, a third circuit connected to the output of said first set of said first and said second circuits, a fourth circuit connected to the output of said second set of said first and said second circuits, a source of reference voltage connected to said third and fourth circuits, a first low pass filter connected to the output of said third circuit, a second low pass filter connected to the output of said fourth circuit, and a differential amplifier connected to the output of said first and second low pass filters for providing a frequency error signal proportional to the difference in frequency between said input signals to said first and second pairs of circuits.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-24 | 1977-12-24 | 1978-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-24 | 1981-12-24 | 1982-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-24 | 1985-12-24 | 1986-06-25 | $7700.00 | Window Closed / Lapsed |