Method and apparatus for decoding a manchester waveform

Claim 1

Apparatus for decoding incoming binary logic derived in the form of a multi-bit series of waves each of said multi-bits having a bit length regularly crossing zero voltage at the center of its length and irregularly crossing said zero voltage at their beginning and end points, the logic of said series being such that the first wave and all subsequent in-phase waves represent one binary logic level while all phase-shifted waves represent another level, said apparatus comprising: means having an input coupled to said incoming serial wave for inverting said series and providing an inverted output, a pair of monostable switches each having a stable state and a triggered quasi-stable state, one of said switches having an input receiving the incoming form of said serial wave and the other an input coupled to and receiving said inverted output, said quasi-stable state of said switches being triggered by the voltage transitions occuring at said zero-crossing center of each of said bit lengths whereby in-phase waves trigger one of the switches and phase-shifted and inverted waves trigger the other to produce output pulses for each bit of the incoming serial wave, means for controlling the length of said output pulses to provide a pulse length slightly longer than a half a bit length whereby output pulses occur only in response to said center crossing voltage transitions, clock means combining said output pulses of said switches for producing a clock puLse for each wave bit, and decoder means responsive to said clock pulses for receiving the binary logic of said incoming serial wave whereby said decoder receives said logic only in response to voltage transitions occurring at the zero-crossing center of each bit length.

Claim 7

A method of decoding an incoming Manchester waveform derived in the form of a combined series of wave bits representing either a ''''zero'''' or a ''''one'''' binary logic level, the ''''zero'''' wave bits being 180* out-of-phase with the ''''one'''' bits and each wave bit having a bit length regularly crossing zero voltage at its center, the method comprising the steps of: initiating a clock pulse of a predetermined length each time said center crosses said zero voltage, and using said initiated pulses to shift said binary logic levels of said incoming waveform into a decoder read-out; said clock pulses having a length slightly greater than one-half a bit length whereby the logic level of each wave bit of said incoming wave is shifted into the read-out and whereby said clock pulses are initiated only in response to said center crossings.

Claim 8

A method of decoding an incoming Manchester waveform derived in the form of a combined series of wave bits representing either a ''''zero'''' or a ''''one'''' binary logic level, the ''''zero'''' wave bits being 180* out-of-phase with the ''''one'''' bits and each wave bit having a bit length regularly crossing zero voltage at its center, the method comprising the steps of: initiating a clock pulse of a predetermined length each time said center crosses said zero voltage, and using said initiated pulses to shift said binary logic levels of said incoming waveform into a decoder read-out; said clock pulses having a length slightly greater than one-half a bit length whereby the logic level of each wave bit of said incoming wave is shifted into the read-out and whereby said clock pulses are initiated only in response to said center crossings.