Noise rejection circuit for digital systems

Claim 2

A noise rejection circuit for digital signals having first and second states comprising: a first lockup counter including a first counter circuit and an input circuit responsive to the first state of said digital signals applied thereto for enabling said first counter circuit during the presence of said signals to count clock pulses and in response to counting a preset number of clock pulses to reach a lockup condition, said lockup counter including an output circuit; a second lockup counter including a second counter circuit and an input circuit responsive to the second state of said digital signals applied thereto for enabling said second counter circuit during the presence of said signals to count clock pulses and in response to counting a preset number of clock pulses to reach a lockup condition; first reset circuit means responsive to the enablement of said first counter circuit for a sufficient duration of time to count a preset number of pulses for applying a signal to reset said second lockup counter, and second reset circuit means responsive to the enablement of said second counter circuit for a sufficient duration of time to count a preset number of pulses for applying a signal to reset said first lockup counter.

Claim 3

A noise rejection circuit as defined in claim 1 wherein: said preset numbers of clock pulses to which said first and second counter circuits count to reach the lockup condition are equal, and said preset numbers to which said first and second reset circuit means Are responsive are equal and less than said preset number of clock pulses to reach the lockup condition.

Claim 4

A noise rejection circuit as defined in claim 2 wherein: said first counter circuit includes a plurality of first flip-flop circuits interconnected so that when enabled said first flip-flop circuits count said preset number of clock pulses to reach the lockup condition; said first lockup counter includes a decoder means responsive to the lockup condition of said first counter circuit and the signal to reset said first lockup counter for resetting the plurality of first flip-flop circuits; said first reset circuit means includes a decoder circuit for generating said signal to reset said second lockup counter when the flip-flop circuits in said first counter circuit reach said preset count for reset; said second counter circuit includes a plurality of second flip-flop circuits interconnected so that when enabled said second flip-flop circuits count said preset number of clock pulses to reach the lockup condition; said second lockup counter includes a decoder means responsive to the lockup condition of said second counter circuit and the signal to reset said second lockup counter for resetting the plurality of second flip-flop circuits, and said second reset circuit means includes a decoder circuit for generating said signal to reset said first lockup counter when the flip-flop circuits in said second counter circuit reach said preset count for reset.

Claim 5

A noise rejection circuit as defined in claim 3 wherein: said input circuit of said first lockup counter includes gating circuit means responsive to the first state of said digital signals for enabling the flip-flop circuits of the first lockup counter to count clock pulses, said gating circuit means connected to said decoder means of said first lockup counter and responsive thereto for resetting said first flip-flop circuits, and said input circuit of said second lockup counter includes second gating circuit means responsive to the second state of said digital signals for enabling the flip-flop circuits of the second lockup counter to count clock pulses, said second gating circuit means connected to said decoder means of said second lockup counter and responsive thereto for resetting said second flip-flop circuits.

Claim 6

A noise rejection circuit as defined in claim 4 including: third reset circuit means receiving said digital signals and responsive to both the first and second lockup counters in the lockup condition for detecting the state of the digital signal and resetting said second lockup counter when the digital signal is in said first state and resetting said first lockup counter when the digital signal is in said second state.

Claim 7

A noise rejection circuit for digital signals having first and second states comprising: first and second lockup counters responsive to the presence of enabling signals applied thereto for counting a preset number of clock pulses to reach a lockup condition and to reset in the event that the enabling signal is removed prior to reaching the lockup condition, at least one of said lockup counters including an output circuit for generating digital output signals; circuit means receiving the digital signals for enabling the first lockup counter in response to one state of said digital signal and enabling the second lockup counter in response to the other state of said digital signals, and reset circuit means interconnecting said first and second lockup counters for resetting one of said lockup counters when the other of said lockup counters has counted a preset number of pulses.

Claim 8

A noise rejection circuit for digital signals having first and second states comprising: first and second lockup counters responsive to the presence of enabling signals applied thereto for counting a preset number of clock pulses to reach a lockup condition and to reset in the event that the enabling signal is removed prior to reaching the lockup condition, at least one of said lockup counters including an output circuit for generating digital output signals; circuit means receiving the digital signals for enabling the first lockup counter in response to one state of said digital signal and enabling the second lockup counter in response to the other state of said digital signals, and reset circuit means interconnecting said first and second lockup counters for resetting one of said lockup counters when the other of said lockup counters has counted a preset number of pulses.

Claim 9

A noise rejection circuit as defined in claim 6 wherein: said preset number of counts for said reset circuit means is less than the preset number of counts for lockup.

Claim 10

A noise rejection circuit as defined in claim 7 wherein: each of said first and second lockup counters includes a plurality of flip-flop circuits wHerein the flip-flops in the lockup counters are interconnected so that when enabled by said circuit means said flip-flop circuits count to said preset number of clock pulses to reach the lockup condition and reset in the event that the flip-flops are disabled prior to reaching the lockup condition, and each of said first and second lockup counters includes a decoder circuit responsive to the lockup condition and the reset signal from said reset circuit means for resetting the flip-flop circuits.

Claim 11

A noise rejection circuit as defined in claim 8 wherein: said reset circuit means includes a separate decoder circuit for monitoring separate ones of said first and second lockup counters for generating reset signals when the flip-flop circuits in the associated ones of said lockup counters reach said preset count for reset.

Claim 12

A noise rejection circuit as defined in claim 9 wherein said circuit means includes: input circuit means for said first lockup counter including a gating circuit responsive to the first state of said digital signals for enabling the flip-flop circuits of the first lockup counter to count clock pulses and responsive to a signal from the reset circuit means decoder circuit monitoring the second lockup counter to reset the first lockup counter flip-flop circuits, and input circuit means for said second lockup counter including a gating circuit responsive to the second state of said digital signals for enabling the flip-flop circuits of the second lockup counter to count clock pulses and responsive to a signal from the reset circuit decoder circuit monitoring the first lockup circuit to reset the second lockup counter flip-flop circuits.

Claim 13

A noise rejection circuit as defined in claim 10 including: reset circuit means responsive to the flip-flop circuits in both the first and second lockup counters being set in the lockup condition for detecting the state of the digital signals and resetting said first lockup counter when the digital signal is in the second state and resetting the second lockup counter when the digital signal is in the first state.

Claim 14

In a system receiving a digital signal having first and second states and including a source of clock pulses having a repetition rate substantially greater than the digital signal, a noise rejection circuit comprising: a first counter connected to said source of clock pulses, first circuit means receiving said digital signal and responsive to said first state thereof for enabling said first counter to count said clock pulses, first gate means connected to said first counter and responsive to a predetermined number of said clock pulses counted by said first counter for generating a first reset pulse; a second counter connected to said source of clock pulses, second circuit means receiving said digital signal and responsive to said second state thereof for enabling said second counter to count said clock pulses, second gate means connected to said second counter and responsive to a predetermined number of said clock pulses counted by said second counter for generating a second reset pulse, fourth gate means having inputs connected to said second counter and said first gate means and responsive to another predetermined number of said clock pulses counted by said second counter and an absence of said first reset pulse for generating a second inhibit-reset signal, said other predetermined number greater than said predetermined number, said second circuit means connected to said fourth gate means and receiving said second inhibit-reset signal, said second circuit means responsive thereto for enabling said second counter to count said clock pulses during an absence of said digital signal of said second state, said fourth gate means and said second circuit means further responsive to said first reset pulse for resetting said second counter; third gate means having inputs connected to said first counter and said second gate means and responsive to another predeterminEd number of said clock pulses counted by said first counter and an absence of said second reset pulse for generating a first inhibit-reset signal, said first circuit means connected to said third gate means and receiving said first inhibit-reset signal, said first circuit means responsive thereto for enabling said first counter to count said clock pulses during an absence of said digital signal of said first state, said third gate means and said first circuit means further responsive to said second reset pulse for resetting said first counter; means connected to at least one of said counters for generating a digital output signal, and a reset circuit means receiving said digital signal and having inputs connected to said third and fourth gate means, and responsive to the presence of both of said first and second inhibit-reset signals for resetting said first counter when said digital signal is in said second state and resetting said second counter when said digital signal is in said first state.

Claim 15

In a system receiving a digital signal having first and second states and including a source of clock pulses having a repetition rate substantially greater than the digital signal, a noise rejection circuit comprising: a first counter connected to said source of clock pulses, first circuit means receiving said digital signal and responsive to said first state thereof for enabling said first counter to count said clock pulses, first gate means connected to said first counter and responsive to a predetermined number of said clock pulses counted by said first counter for generating a first reset pulse; a second counter connected to said source of clock pulses, second circuit means receiving said digital signal and responsive to said second state thereof for enabling said second counter to count said clock pulses, second gate means connected to said second counter and responsive to a predetermined number of said clock pulses counted by said second counter for generating a second reset pulse, fourth gate means having inputs connected to said second counter and said first gate means and responsive to another predetermined number of said clock pulses counted by said second counter and an absence of said first reset pulse for generating a second inhibit-reset signal, said other predetermined number greater than said predetermined number, said second circuit means connected to said fourth gate means and receiving said second inhibit-reset signal, said second circuit means responsive thereto for enabling said second counter to count said clock pulses during an absence of said digital signal of said second state, said fourth gate means and said second circuit means further responsive to said first reset pulse for resetting said second counter; third gate means having inputs connected to said first counter and said second gate means and responsive to another predeterminEd number of said clock pulses counted by said first counter and an absence of said second reset pulse for generating a first inhibit-reset signal, said first circuit means connected to said third gate means and receiving said first inhibit-reset signal, said first circuit means responsive thereto for enabling said first counter to count said clock pulses during an absence of said digital signal of said first state, said third gate means and said first circuit means further responsive to said second reset pulse for resetting said first counter; means connected to at least one of said counters for generating a digital output signal, and a reset circuit means receiving said digital signal and having inputs connected to said third and fourth gate means, and responsive to the presence of both of said first and second inhibit-reset signals for resetting said first counter when said digital signal is in said second state and resetting said second counter when said digital signal is in said first state.