Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
76 words
Apparatus comprising a plurality of serially-connected converter circuits and a plurality of loads serially connected with said converter circuits, each of said converter circuits having a feedback control circuit providing additive simultaneous effect and continuous inverse controlled relationship of output current and voltage during the normal mode of regulation of said circuit, each of said circuits having means for providing a plurality of other modes of regulation respectively effective at differing limits of said normal mode.
Claim 2
Dependent Claim
76 words
Apparatus comprising a plurality of serially-connected converter circuits and a plurality of loads serially connected with said converter circuits, each of said converter circuits having a feedback control circuit providing additive simultaneous effect and continuous inverse controlled relationship of output current and voltage during the normal mode of regulation of said circuit, each of said circuits having means for providing a plurality of other modes of regulation respectively effective at differing limits of said normal mode.
Claim 3
Dependent Claim
68 words
Apparatus according to claim 1 in whIch the means for providing a plurality of other modes of regulation comprises means for regulating the output current to be substantially constant when the output current rises beyond the high current limit of the normal mode and means for regulating the output voltage to be substantially constant when the output voltage rises beyond the high voltage limit of the normal mode.
Claim 4
Dependent Claim
103 words
Apparatus according to claim 2 in which the feedback control circuit includes means for sensing the output current and generating a first signal directly related thereto, means for sensing the output voltage and generating a second signal directly related thereto, means for generating a third signal directly related to the first and second signals, means for comparing said first, second and third signals to selected reference values thereof to generate first, second and third error signals respectively, and means including an OR gate for applying the largest of said error signals of a selected polarity to switch the state of said converter circuit.
Claim 5
Dependent Claim
88 words
Apparatus according to claim 3 including means for shutting down each of the converter circuits in response to a fourth signal from any of said converter circuits, means for generating the fourth signal when the second signal related to output voltage exceeds a variable reference signal, and means for generating said variable reference signal as the sum of a constant value and a signal proportional to a fifth signal related to output current, the presence of the fourth signal being indicative of an excessive value of load impedance.
Claim 6
Dependent Claim
223 words
Apparatus comprising a source of dc input voltage, a transistor inverter circuit for converting said voltage to an ac voltage at a constant frequency and with zero voltage value during a portion of each half-cycle, means for rectifying and filtering said ac voltage to produce a dc output voltage, and means for varying the zero-voltage portion of each half-cycle, comprising first means for sensing the dc output voltage, second means for sensing the dc output current, means responsive to said first and second sensing means for generating a first signal that varies in direct relationship with said output voltage and in direct relationship with said output current, means responsive to said first sensing means for generating a second signal that varies in direct relationship only with said output voltage, means responsive to said second sensing means for generating a third signal that varies in direct relationship only with said output current, and means including an OR gate coupled between said generating means and said inverter circuit for transmitting the first signal to control the inverter continuously throughout a normal range of said first signal, whereby a continuous inverse relationship between the dc output voltage and dc output current results, and for transmitting to control the inverter whichever of said second or third signals is increasing beyond the respective limits of said normal range.
Claim 7
Dependent Claim
223 words
Apparatus comprising a source of dc input voltage, a transistor inverter circuit for converting said voltage to an ac voltage at a constant frequency and with zero voltage value during a portion of each half-cycle, means for rectifying and filtering said ac voltage to produce a dc output voltage, and means for varying the zero-voltage portion of each half-cycle, comprising first means for sensing the dc output voltage, second means for sensing the dc output current, means responsive to said first and second sensing means for generating a first signal that varies in direct relationship with said output voltage and in direct relationship with said output current, means responsive to said first sensing means for generating a second signal that varies in direct relationship only with said output voltage, means responsive to said second sensing means for generating a third signal that varies in direct relationship only with said output current, and means including an OR gate coupled between said generating means and said inverter circuit for transmitting the first signal to control the inverter continuously throughout a normal range of said first signal, whereby a continuous inverse relationship between the dc output voltage and dc output current results, and for transmitting to control the inverter whichever of said second or third signals is increasing beyond the respective limits of said normal range.
Claim 8
Dependent Claim
67 words
Apparatus according to claim 5 including means responsive to said first sensing means and to additional means for sensing output current for generating a fourth signal that varies according to the difference of a function of the output voltage and a function of the output current, and means for applying the fourth signal to shut down the transistor inverter whenever the fourth signal exceeds a selected limit.