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US3818243A
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Error correction by redundant pulse powered circuits
Assignee: Massachusetts Institute of Technology
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Filing: 1973-01-12
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Granted: 1974-06-18
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Expires: 1993-01-12
Abstract
Abstract A redundant circuit which utilizes pulsed power techniques to achieve low power and high reliability by automatic error correction, through the interconnection of capacitors of the various redundant circuit elements.
Inventors
- 👤 Mahon R Mc
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:31
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/187; H; H03; H03K; H03K19/00; H03K19/003; H03K19/00392
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
134 words
A pulse power redundant circuit comprising: a multiplicity of digital flip-flop elements, said digital elements forming at least three redundant channels for input pulses, a source of pulsed power connected to the power input terminal of each flip-flop element for periodically simultaneously energizing all of said redundant digital elements, each of said elements having a pair of capacitors for storing the state of said digital element one at the input terminal and one at the output terminal of each element and a capacitor coupling each storage capacitor at the input terminal and output terminal of each element to the corresponding storage capacitor at the input and output terminals, respectively, of said redundant digital elements, whereby said redundant elements are all maintained in the binary state of the majority of said elements between power pulses.
Claim 2
Dependent Claim
134 words
A pulse power redundant circuit comprising: a multiplicity of digital flip-flop elements, said digital elements forming at least three redundant channels for input pulses, a source of pulsed power connected to the power input terminal of each flip-flop element for periodically simultaneously energizing all of said redundant digital elements, each of said elements having a pair of capacitors for storing the state of said digital element one at the input terminal and one at the output terminal of each element and a capacitor coupling each storage capacitor at the input terminal and output terminal of each element to the corresponding storage capacitor at the input and output terminals, respectively, of said redundant digital elements, whereby said redundant elements are all maintained in the binary state of the majority of said elements between power pulses.
Claim 3
Dependent Claim
26 words
A pulse power redundant circuit according to claim 1 wherein, said corresponding capacitors for storing the state of each element are all equal to each other.
Claim 4
Dependent Claim
26 words
A pulse power redundant circuit according to claim 2 wherein, all said elements are the same and all the coupling capacitors are equal to each other.
Claim 5
Dependent Claim
23 words
A binary redundant circuit as in claim 1 wherein, all the coupling capacitors which couple corresponding storage capacitors are equal to each other.
Claim 6
Dependent Claim
118 words
A binary redundant circuit comprising, a multiplicity of digital flip-flop elements, said digital elements forming at least three redundant channels for input pulses, a source of input power pulses, connected to the input power terminal of each digital element for periodically energizing all of said redundant digital elements, each of said elements having a pair of capacitors for storing the binary state thereof, one capacitor at the input terminal and one at the output terminal of each element and separate capacitors connected between each storage capacitor of each element to the corresponding storage capacitor of each other of said redundant elements, whereby said redundant elements are all maintained in the binary state of the majority of said elements.
Claim 7
Dependent Claim
118 words
A binary redundant circuit comprising, a multiplicity of digital flip-flop elements, said digital elements forming at least three redundant channels for input pulses, a source of input power pulses, connected to the input power terminal of each digital element for periodically energizing all of said redundant digital elements, each of said elements having a pair of capacitors for storing the binary state thereof, one capacitor at the input terminal and one at the output terminal of each element and separate capacitors connected between each storage capacitor of each element to the corresponding storage capacitor of each other of said redundant elements, whereby said redundant elements are all maintained in the binary state of the majority of said elements.
Claim 8
Dependent Claim
28 words
A binary redundant circuit as in claim 5 wherein, all the storage capacitors are equal to each other and all the coupling capacitors are equal to each other.
Claim 9
Dependent Claim
25 words
A binary redundant circuit as in claim 5 wherein, all the redundant elements are identical and all the coupling capacitors are equal to each other.
Claim 10
Dependent Claim
44 words
A binary redundant circuit as in claim 5 and further including a source of pulse power for energizing all of said elements simultaneously, whereby all of said redundant elements are maintained in the binary state of the majority of said elements between input pulses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-17 | 1977-12-17 | 1978-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-17 | 1981-12-17 | 1982-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-17 | 1985-12-17 | 1986-06-18 | $7700.00 | Window Closed / Lapsed |