Abstract An address generator for applying a sequence of address bit signals a communication channel to successively define a plurality of different multi-bit addresses. The address generator includes a sequence logic network comprised of an N stage shift register which, with a minimum hardware configuration, produces an M-bit sequence defining 2N unique N-bit subsequences. The minimum hardware configuration includes a feedback network for normally entering the complement of stage N into stage 1. When so doing would produce a repeat state, then instead, the output of stage N is entered into stage 1 without inversion. Thus, the feedback network need merely recognize when a repeat state is about to occur and abort it by forcing a previously undefined state.
Apparatus for generating a sequence of M bits consisting of unique subsequences of N adjacent bits, said apparatus comprising: N binary storage stages each having data input and output terminals and an input control terminal; means coupling the data output terminal of each of stages 1 through (N-1) to the data input terminal of the succeeding stage; a source of periodic timing pulses; means connecting said source of timing pulses to all of said input control terminals; first feeDback logic means for coupling a true representation of the bit stored in stage N to the data input terminal of stage 1; second feedback logic means for coupling a complementary representation of the bit stored in stage N to the data input terminal of stage 1; and logic means responsive to the bits stored in stages 1 through (N-1) for selectively enabling either said first or second feedback logic means.
Claim 2
Dependent Claim
149 words
Apparatus for generating a sequence of M bits consisting of unique subsequences of N adjacent bits, said apparatus comprising: N binary storage stages each having data input and output terminals and an input control terminal; means coupling the data output terminal of each of stages 1 through (N-1) to the data input terminal of the succeeding stage; a source of periodic timing pulses; means connecting said source of timing pulses to all of said input control terminals; first feeDback logic means for coupling a true representation of the bit stored in stage N to the data input terminal of stage 1; second feedback logic means for coupling a complementary representation of the bit stored in stage N to the data input terminal of stage 1; and logic means responsive to the bits stored in stages 1 through (N-1) for selectively enabling either said first or second feedback logic means.
Claim 3
Dependent Claim
52 words
The apparatus of claim 1 including means normally enabling said second feedback logic means and disabling said first feedback logic means; and wherein said logic means is responsive to particular bit patterns stored in stages 1 through (N-1) for disabling said second feedback logic means and enabling said first feedback logic means.