Noise suppression circuit

Claim 2

A noise suppression circuit comprising in combination a first transistor the emitter of which is connected to an input lead means to a working circuit and the collector of which is connected to a first reference potential; a second transistor the emitter of which is connected to said input lead means, the collector of which is connected to a second reference potential and the base of which is connected to the base of said first transistor; wherein said input lead means comprises an input lead, and output lead and impedance means connecting said output lead to said input lead, said emitter of said first transistor being connected to said impedance means and said emitter of said second transistor being connected to the output lead of said input lead means.

Claim 3

Structure as in claim 1 wherein said first transistor comprises a PNP transistor, said second transistor comprises an NPN transistor, and said impedance means comprises a resistor.

Claim 4

Structure as in claim 2 wherein said resistor comprises a portion of the emitter region of said first transistor.

Claim 5

Structure as in claim 2 wherein said first reference potential is ground and said second reference potential is a selected positive voltage.

Claim 6

Structure as in claim 2 wherein said first reference potential is a selected negative voltage and said second reference potential is at ground.

Claim 7

Structure as in claim 2 wherein said first reference potential has a value less than said second reference potential.

Claim 8

Semiconductor structure comprising: a. a substrate of semiconductor material of a first conductivity type; b. a layer of monocrystalline semiconductor material of a second conductivity type formed on said substrate; c. a first region of said first conductivity type formed in said layer of semiconductor material adjacent one portion of its top surface; d. a second region of said first conductivity type formed in asid layer of semiconductor material adjacent another portion of its top surface; e. a region of said second conductivity type formed in said second region of said first conductivity type; f. conductive means connecting said region of said second conDuctivity type to said first region of said first conductivity type; g. conductive means connecting said layer of monocrystalline semiconductor material to said second region; h. an input lead connected to said first region; and i. an output lead means connected to another portion of said first region, whereby said first region comprises both the emitter region of a transistor and a resistor between said input lead and said output lead.

Claim 9

Semiconductor structure comprising: a. a substrate of semiconductor material of a first conductivity type; b. a layer of monocrystalline semiconductor material of a second conductivity type formed on said substrate; c. a first region of said first conductivity type formed in said layer of semiconductor material adjacent one portion of its top surface; d. a second region of said first conductivity type formed in asid layer of semiconductor material adjacent another portion of its top surface; e. a region of said second conductivity type formed in said second region of said first conductivity type; f. conductive means connecting said region of said second conDuctivity type to said first region of said first conductivity type; g. conductive means connecting said layer of monocrystalline semiconductor material to said second region; h. an input lead connected to said first region; and i. an output lead means connected to another portion of said first region, whereby said first region comprises both the emitter region of a transistor and a resistor between said input lead and said output lead.

Claim 10

Structure as in claim 7 wherein said first conductivity type is P type conductivity and said second conductivity type is N type conductivity.

Claim 11

Structure as in claim 7 wherein said semiconductor material is silicon.

Claim 12

Semiconductor structure comprising: a. a substrate of semiconductor material of a first conductivity type; b. a layer of monocrystalline semiconductor material of a second conductivity type formed on said substrate; c. a first region of second conductivity type formed in the top surface of said substrate of semiconductor material adjacent said layer, said first region having an impurity concentration such that it has a low resistivity; d. a first region of said first conductivity type formed in said layer of semiconductor material adjacent its top surface; e. a second region of said first conductivity type formed in said layer of semiconductor material adjacent another portion of its top surface; f. a second region of said second conductivity type formed in said first region of said first conductivity type adjacent its top surface; g. a third region of said second conductivity type formed in said second region of said first conductivity type adjacent its top surface; h. conductive means interconnecting said first region of said first conductivity type with said third region of said second conductivity type; i. conductive means interconnecting said second region of said first conductivity type with said second region of said second conductivity type; j. an input lead connected to one portion of said first region of said first conductivity type; k. an output lead connected to another portion of said first region of said first conductivity type, whereby said first region of said first conductivity type comprises a resistor and said third region of said second conductivity type comprises the emitter of a transistor; l. a source of reference potential; and m. conductive means connecting said source of reference potential to said layer of monocrystalline semiconductor material.

Claim 13

Semiconductor structure comprising: a. a substrate of semiconductor material of a first conductivity type; b. a layer of monocrystalline semiconductor material of a second conductivity type formed on said substrate; c. a first region of second conductivity type formed in the top surface of said substrate of semiconductor material adjacent said layer, said first region having an impurity concentration such that it has a low resistivity; d. a first region of said first conductivity type formed in said layer of semiconductor material adjacent its top surface; e. a second region of said first conductivity type formed in said layer of semiconductor material adjacent another portion of its top surface; f. a second region of said second conductivity type formed in said first region of said first conductivity type adjacent its top surface; g. a third region of said second conductivity type formed in said second region of said first conductivity type adjacent its top surface; h. conductive means interconnecting said first region of said first conductivity type with said third region of said second conductivity type; i. conductive means interconnecting said second region of said first conductivity type with said second region of said second conductivity type; j. an input lead connected to one portion of said first region of said first conductivity type; k. an output lead connected to another portion of said first region of said first conductivity type, whereby said first region of said first conductivity type comprises a resistor and said third region of said second conductivity type comprises the emitter of a transistor; l. a source of reference potential; and m. conductive means connecting said source of reference potential to said layer of monocrystalline semiconductor material.

Claim 14

Structure as in claim 10 wherein said first conductivity type is P type conductivity and said second conductivity type is N type conductivity.

Claim 15

Structure as in claim 10 wherein said layer of monocrystalline semiconductor material has formed in it P type diffused isolation regions extending to said substrate thereby to isolate the structure formed in said layer of monocrystalline semiconductor material from adjacent regions of said layer of monocrystalline semiconductor material.

Claim 16

Semiconductor structure comprising: a substrate of semiconductor material of a first conductivity type; a layer of monocrystalline semiconductor material of a second conductivity type formed on said substrate; isolation regions of said first conductivity type extending through said layer of monocrystalline semiconductor material to said substrate thereby to form at least a first pocket and a second pocket of semiconductor material of a second conductivity type in said layer, said first pocket being substantially electrically isolated from said second pocket; a first region of said first conductivity type formed in said first pocket adjacent to the top surface of said first pocket; a second region of said first conductivity type formed in said second pocket adjacent a portion of the top surface of said second pocket; a first region of second conductivity type formed in said substrate beneath said second pocket of semiconductor material, the iMpurity concentration of said first region being such that said first region has a low resistivity; a second region of second conductivity type formed in said second region of said first conductivity type adjacent the top surface of said second region of said first conductivity type; conductive means connecting said second region of said first conductivity type to the semiconductor material comprising said first pocket; conductive means connecting said first region of said first conductivity type to said second region of said second conductivity type; an input lead connected to a portion of said first region of said first conductivity type; an output lead connected to another portion of said first region of said first conductivity type whereby said first region of said first conductivity type comprises both a resistor and the emitter of a first transistor, said first transistor having a base region in said first pocket and a collector region in said substrate; a source of reference potential; and means connecting said source of reference potential to said second pocket of semiconductor material.

Claim 17

Semiconductor structure comprising: a substrate of semiconductor material of a first conductivity type; a layer of monocrystalline semiconductor material of a second conductivity type formed on said substrate; isolation regions of said first conductivity type extending through said layer of monocrystalline semiconductor material to said substrate thereby to form at least a first pocket and a second pocket of semiconductor material of a second conductivity type in said layer, said first pocket being substantially electrically isolated from said second pocket; a first region of said first conductivity type formed in said first pocket adjacent to the top surface of said first pocket; a second region of said first conductivity type formed in said second pocket adjacent a portion of the top surface of said second pocket; a first region of second conductivity type formed in said substrate beneath said second pocket of semiconductor material, the iMpurity concentration of said first region being such that said first region has a low resistivity; a second region of second conductivity type formed in said second region of said first conductivity type adjacent the top surface of said second region of said first conductivity type; conductive means connecting said second region of said first conductivity type to the semiconductor material comprising said first pocket; conductive means connecting said first region of said first conductivity type to said second region of said second conductivity type; an input lead connected to a portion of said first region of said first conductivity type; an output lead connected to another portion of said first region of said first conductivity type whereby said first region of said first conductivity type comprises both a resistor and the emitter of a first transistor, said first transistor having a base region in said first pocket and a collector region in said substrate; a source of reference potential; and means connecting said source of reference potential to said second pocket of semiconductor material.

Claim 18

Structure as in claim 13 wherein said first conductivity type is P type conductivity and said second conductivity type is N type conductivity.

Claim 19

Structure as in claim 14 wherein said substrate is connected to a second reference potential of a value less than said first reference potential.

Claim 20

Structure as in claim 15 wherein said second reference potential is ground and said first reference potential is a selected positive voltage.

Claim 21

A noise suppression circuit comprising in combination: a transistor, the emitter of which is connected to an input lead means of a working circuit and the collector of which is connected to a reference potential; and a diode connecting the base of said transistor to the emitter of said transistor for providing a low impedance path to discharge collector-base junction capacitance of said transisotr when the base-emitter junction of said transistor is reverse biased; wherein said input lead means comprises an input lead, an output lead, and an impedance means connecting said output lead to said input lead, said emitter of said transistor being connected to said impedance means and one lead of said diode being connected to the output lead of said input means.

Claim 22

A noise suppression circuit comprising in combination: a transistor, the emitter of which is connected to an input lead means of a working circuit and the collector of which is connected to a reference potential; and a diode connecting the base of said transistor to the emitter of said transistor for providing a low impedance path to discharge collector-base junction capacitance of said transisotr when the base-emitter junction of said transistor is reverse biased; wherein said input lead means comprises an input lead, an output lead, and an impedance means connecting said output lead to said input lead, said emitter of said transistor being connected to said impedance means and one lead of said diode being connected to the output lead of said input means.

Claim 23

Structure as in claim 17 wherein said transistor is a PNP transistor and said diode is connected so as to provide a low impedance path to discharge the collector-base junction capacitance of said transistor when said base is at a potential higher than said emitter.

Claim 24

Structure as in claim 17 wherein said transistor is an NPN transistor and said diode is connected so as to provide a low impedance path to discharge the collector-base junction capacitance of said transistor when said base is at a potential lower than said emitter.