US3816728A
Expired / Lapsed
US
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Modulo 9 residue generating and checking circuit
Assignee: International Business Machines Corp
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Filing: 1972-12-14
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Granted: 1974-06-11
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Expires: 1992-12-14
Abstract
Abstract A modulo 9 residue generating and checking circuit for checking the accuracy of decimal addition operations in digital computers and other data processing equipment. A set of data words each representing a number to be added is transmitted to a multinumber adder which adds the words and provides a smaller set of words as a subtotal sum. The bits of the subtotal words are then divided into two groups. Each group of bits is fed to a respective modulo 9 residue generator which calculates the modulo 9 residue of the group. The two resulting residues are then fed to a third modulo 9 residue generator which calculates the modulo 9 residue of the sum of the two residues, thereby providing the modulo 9 residue of the sum of the original set of data words. This result may then be compared in the conventional manner with the modulo 9 residue of the sum resulting from the addition operation to be checked.
Inventors
- 👤 T Chen
- 👤 I Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:55
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/104
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
114 words
A residue calculating circuit for calculating the residue of the sum of an augend and a plurality of addends and comprising multi-number adder means for adding an augend data word and a plurality of addend data words simultaneously in parallel to provide a subtotal sum in the form of a set of words each having a predetermined number of bits, a residue generator, and means for transmitting said subtotal sum words simultaneously in parallel to said residue generator, said residue generator including means for processing said set of subtotal sum words simultaneously in parallel to calculate the residues of said subtotal sum words and to calculate the residue of the sum of said residues.
Claim 2
Dependent Claim
114 words
A residue calculating circuit for calculating the residue of the sum of an augend and a plurality of addends and comprising multi-number adder means for adding an augend data word and a plurality of addend data words simultaneously in parallel to provide a subtotal sum in the form of a set of words each having a predetermined number of bits, a residue generator, and means for transmitting said subtotal sum words simultaneously in parallel to said residue generator, said residue generator including means for processing said set of subtotal sum words simultaneously in parallel to calculate the residues of said subtotal sum words and to calculate the residue of the sum of said residues.
Claim 3
Dependent Claim
52 words
A circuit as recited in claim 1 wherein said multi-number adder means comprises a plurality of column adders each corresponding to the bits of a respective predetermined weight of said augend and addends, each column adder comprising means for adding the bits of the respective predetermined weight of said augend and addends.
Claim 4
Dependent Claim
18 words
A circuit as recited in claim 1 wherein said residue generator means comprises a read only memory circuit.
Claim 5
Dependent Claim
18 words
A circuit as recited in claim 3 wherein said read only memory circuit comprises an array logic circuit.
Claim 6
Dependent Claim
61 words
A circuit as recited in claim 1 wherein said multi-number adder means comprises a plurality of column adders each corresponding to the bits of a respective predetermined weight of said augend and addends, each column adder comprising means for adding the bits of the respective predetermined weight of said augend and addends, said residue generator means comprising an array logic circuit.
Claim 7
Dependent Claim
22 words
A circuit as recited in claim 1 wherein said residue generator means comprises means for generating residues with respect to modulus 9.
Claim 8
Dependent Claim
17 words
A circuit as recited in claim 6 wherein said residue generator means comprises an array logic circuit.
Claim 9
Dependent Claim
52 words
A circuit as recited in claim 7 wherein said multi-number adder means comprises a plurality of column adders each corresponding to the bits of a respective predetermined weight of said augend and addends, each column adder comprising means for adding the bits of the respective predetermined weight of said augend and addends.
Claim 10
Dependent Claim
55 words
The residue Calculating circuit as recited in claim 1 and further including adder means for calculating the sum of said augend and plurality of addends, residue calculator means for calculating the residue of said sum, and comparator means for comparing the result of said residue calculator means with the result of said residue calculating circuit.
Claim 11
Dependent Claim
52 words
A circuit as recited in claim 9 wherein said multi-number adder means comprises a plurality of column adders each corresponding to the bits of a respective predetermined weight of said augend and addends, each column adder comprising means for adding the bits of the respective predetermined weight of said augend and addends.
Claim 12
Dependent Claim
18 words
A circuit as recited in claim 10 wherein said residue generator means comprises a read only memory circuit.
Claim 13
Dependent Claim
18 words
A circuit as recited in claim 11 wherein said read only memory circuits comprises an array logic circuit.
Claim 14
Dependent Claim
61 words
A circuit as recited in claim 10 wherein said multi-number adder means comprises a plurality of column adders each corresponding to the bits of a respective predetermined weight of said augend and addends, each column adder comprising means for adding the bits of the respective predetermined weight of said augend and addends. said residue generator means comprising an array logic circuit.
Claim 15
Dependent Claim
22 words
A circuit as recited in claim 10 wherein said residue generating means comprises means for generating residues with respect to modulus 9.
Claim 16
Dependent Claim
17 words
A circuit as recited in claim 14 wherein said residue generator means comprises an array logic circuit.
Claim 17
Dependent Claim
52 words
A circuit as recited in claim 15 wherein said multi-number adder means comprises a plurality of column adders each corresponding to the bits of a respective predetermined weight of said augend and addends, each column adder comprising means for adding the bits of the respective predetermined weight of said augend and addends.
Claim 18
Dependent Claim
148 words
A residue calculating circuit for calculating the residue of the sum of an augend and a plurality of addends and comprising multi-number adder means for simultaneously adding an augend data word and a plurality of addend data words to provide a subtotal sum in the form of a plurality of words each having a predetermined number of bits, means for dividing said bits of said subtotal sum words into a set of groups with each group including the bits of a predetermined range of weights, a set of residue generators each corresponding to a respective one of said groups of bits, means for transmitting each group of bits to its respective residue generator, each residue generator including means for generating the residue of the respective group of bits, and additional residue generator means for generating the residue of the sum of said residues of the groups of bits.
Claim 19
Dependent Claim
148 words
A residue calculating circuit for calculating the residue of the sum of an augend and a plurality of addends and comprising multi-number adder means for simultaneously adding an augend data word and a plurality of addend data words to provide a subtotal sum in the form of a plurality of words each having a predetermined number of bits, means for dividing said bits of said subtotal sum words into a set of groups with each group including the bits of a predetermined range of weights, a set of residue generators each corresponding to a respective one of said groups of bits, means for transmitting each group of bits to its respective residue generator, each residue generator including means for generating the residue of the respective group of bits, and additional residue generator means for generating the residue of the sum of said residues of the groups of bits.
Claim 20
Dependent Claim
52 words
A circuit as recited in claim 17 wherein said multi-number adder means comprises a plurality of column adders each corresponding to the bits of a respective predetermined weight of said augend and addends, each column adder comprising means for adding the bits of the respective predetermined weight of said augend and addends.
Claim 21
Dependent Claim
18 words
A circuit as recited in claim 18 wherein each of said residue generator means comprises a memory circuit.
Claim 22
Dependent Claim
18 words
A circuit as recited in claim 18 wherein each of said memory circuits comprises an array logic circuit.
Claim 23
Dependent Claim
63 words
A circuit as recited in claim 17 wherein said multi-number adder means comprises a plurality of column adders each corresponding to the bits of a respective predetermined weight of said augend and addends, each column adder comprising means for adding the bits of the respective predetermined weight of said augend and addends, each of said residue generator means comprising an array logic circuit.
Claim 24
Dependent Claim
24 words
A circuit as recited in claim 17 wherein each of said residue generating means comprises means for generating residues with respect to modulus 9.
Claim 25
Dependent Claim
19 words
A circuit as recited in claim 22 wherein each of said residue generator means comprises an array logic circuit.
Claim 26
Dependent Claim
52 words
A circuit as recited in claim 23 wherein said multi-number adder means comprises a plurality of column adders each corresponding to the bits of a respective predetermined weight of said augend and addends, each column adder comprising means for adding the bits of the respective predetermined weight of said augend and addends.
Claim 27
Dependent Claim
55 words
The residue calculating circuit as recited in claim 17 and further including adder means for calculating the sum of said augend and plurality of addends, residue calculator means for calculating the residue of said sum, and comparator means for comparing the result of said residue calculator means with the result of said residue calculating circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-10 | 1977-12-10 | 1978-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-10 | 1981-12-10 | 1982-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-10 | 1985-12-10 | 1986-06-11 | $7700.00 | Window Closed / Lapsed |