Patent US3815124A successfully refreshed from Google Patents.
US3815124A
Expired / Lapsed
US
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Analog to digital converter
Assignee: Westinghouse Electric Corp
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Filing: 1973-01-16
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Granted: 1974-06-04
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Expires: 1993-01-16
Abstract
Abstract An electronic analog to digital converter which samples and quantizes an analog signal in two signal channels respectively providing digital words corresponding to the envelope of the analog input signal and an amplitude normalized analog signal. The normalized or waveform signal defines the waveform structure which contains the analog signal frequency components above that contained in the envelope signal. The envelope digital word for a given time sample multiplied by the waveform digital word for that same time sample provides a digital word corresponding to the analog input signal.
Inventors
- 👤 J Brewer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:00
CPC Classifications
H; H03; H03M; H03M1/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
384 words
A dual channel analog to digital signal converter comprising in combination: input signal means coupled to an analog input signal and providing two separate channel signal paths; circuit means responsive to the envelope of said analog input signal, coupled to one signal path and providing an envelope signal; first analog to digital conversion means coupled to said circuit means and being responsive to said envelope signal to provide a time sampled portion of said envelope signal and a first digital output word substantially corresponding to said envelope signal, and additionally including control circuit means providing a timing control signal for synchronously operating a second analog to digital converter at predetermined sampling time intervals; gain switching circuit means coupled to the other signal path and said first analog to digital conversion means, receiving a respective input therefrom of said analog input signal and said time sampled portion of said envelope signal and being operable to simultaneously change the amplitudes of both the analog input signal and the time sampled portion of said envelope signal by a predetermined gain factor in response to the amplitude of said sampled time portion of said envelope signal received from said first conversion means and providing a pair of output signals respectively corresponding to a gain varied analog input signal and a gain varied time sampled portion of said envelope signal; signal normalization means coupled to said gain switching circuit means and receiving as inputs said pair of output signals, said gain varied time sampled portion of said envelope signal serving as a normalization reference signal whereupon an analog waveform output signal is generated therein corresponding to the ratio of said gain varied analog input signal to said gain varied time sampled portion of said envelope signal; and second analog to digital conversion means coupled to said signal normalization means and said first analog to digital conversion means being responsive to said waveform output signal and operated in timed relationship with said first analog to digital conversion means by said timing control signal to provide a separate and distinct second digital output word time related to said first digital output word and corresponding to said waveform signal; said first and second digital output words being adapted to be multiplied together to provide a digital version of said analog input signal.
Claim 2
Dependent Claim
384 words
A dual channel analog to digital signal converter comprising in combination: input signal means coupled to an analog input signal and providing two separate channel signal paths; circuit means responsive to the envelope of said analog input signal, coupled to one signal path and providing an envelope signal; first analog to digital conversion means coupled to said circuit means and being responsive to said envelope signal to provide a time sampled portion of said envelope signal and a first digital output word substantially corresponding to said envelope signal, and additionally including control circuit means providing a timing control signal for synchronously operating a second analog to digital converter at predetermined sampling time intervals; gain switching circuit means coupled to the other signal path and said first analog to digital conversion means, receiving a respective input therefrom of said analog input signal and said time sampled portion of said envelope signal and being operable to simultaneously change the amplitudes of both the analog input signal and the time sampled portion of said envelope signal by a predetermined gain factor in response to the amplitude of said sampled time portion of said envelope signal received from said first conversion means and providing a pair of output signals respectively corresponding to a gain varied analog input signal and a gain varied time sampled portion of said envelope signal; signal normalization means coupled to said gain switching circuit means and receiving as inputs said pair of output signals, said gain varied time sampled portion of said envelope signal serving as a normalization reference signal whereupon an analog waveform output signal is generated therein corresponding to the ratio of said gain varied analog input signal to said gain varied time sampled portion of said envelope signal; and second analog to digital conversion means coupled to said signal normalization means and said first analog to digital conversion means being responsive to said waveform output signal and operated in timed relationship with said first analog to digital conversion means by said timing control signal to provide a separate and distinct second digital output word time related to said first digital output word and corresponding to said waveform signal; said first and second digital output words being adapted to be multiplied together to provide a digital version of said analog input signal.
Claim 3
Dependent Claim
25 words
The combination as defined in claim 1 wherein: said input signal means additionally includes signal rectifier means; and said circuit means comprises an envelope detector.
Claim 4
Dependent Claim
17 words
The combination as defined by claim 2 wherein said signal rectifier means comprises full wave rectifier means.
Claim 5
Dependent Claim
27 words
The combination as defined by claim 2 wherein said first analog to digital conversion means comprises a successive approximation analog to digital converter including signal sampling means.
Claim 6
Dependent Claim
108 words
The combination as defined by claim 2 wherein said analog input signal normalization means comprises a voltage divider network coupled between said gain varied time sampled analog envelope signal and a point of reference potential for providing a plurality of voltage reference levels, a plurality of dual input voltage comparator circuits each having one input commonly coupled to the gain varied rectified analog input signal and the other input to a separate reference voltage level of said voltage divider network and providing respective output signals from said comparator circuits corresponding to the ratio of the rectified analog input signal to fractional parts of said sampled analog envelope signal.
Claim 7
Dependent Claim
74 words
The signal converter as defined by claim 5 wherein said second analog to digital conversion means includes digital latch circuit means coupled to the respective outputs of said plurality of voltage comparator circuit means and additionally including circuit means for being selectively enabled by said timing control signal from said first analog to digital converter, and digital encoder circuit means coupled to said digital latch circuit means for generating said second digital output word.
Claim 8
Dependent Claim
16 words
The converter as defined by claim 6 wherein said digital encoder comprises a two''s complement encoder.
Claim 9
Dependent Claim
37 words
The converter as defined by claim 7 and additionally including synchronized delay register means, selectively enabled by said control circuit of said first analog to digital converter means, coupled to the output of said two''s complement encoder.
Claim 10
Dependent Claim
17 words
The converter as defined by claim 1 wherein said detector circuit means comprises an averaging detector circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-03 | 1977-12-03 | 1978-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-03 | 1981-12-03 | 1982-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-03 | 1985-12-03 | 1986-06-04 | $7700.00 | Window Closed / Lapsed |