Zero suppressor circuit

Claim 1

A zero suppressor circuit comprising; A first shift register for storing digital numerical information in a series of bit positions of different significance; a second shift register having an input terminal, connected to receive the contents stored in said first shift register as transferred serially from the least significant digit thereof, said second shift register being arranged for storing a logic code ''''1'''' when a transferred digit is a numerical value other than zero and for storing another logic Code ''''0'''' when the transferred digit is zero; a first recirculating loop connected to recirculate the logic codes from the least significant bit position to the input terminal of the most significant bit position of the second shift register; a second recirculating loop connected to recirculate the logic codes from the least significant bit position to the second most significant bit position of said second shift register; and AND gate means, having one input terminal connected to receive an output from the most significant bit position of said second register and an output from the least significant bit position of said second register through said second recirculating loop, said AND gate means having another input terminal connected to receive a control signal, the output of said AND gate means being connected to the second most significant bit position of said second register; the logic code ''''0'''' of a bit position where the significant bit zero exists being thereby converted to the logic code ''''1'''' when the logic code ''''1'''' exists in a bit position next to and higher than a bit position where the significant bit zero to be displayed exists, and means operative to recirculate the logic codes stored in said second register to repeat the abovedescribed procedure thereby to discriminate the digits to be displayed from other digits to be suppressed of said first shift register.