Apparatus and method for a memory partial-write of error correcting encoded data

Claim 2

In combination with a data processing unit, a memory module comprising: memory element means for storing groups of signals; register meaNs coupled to said memory element means and to said data processing unit for temporarily storing a combination group of data signals, said combination group of signals consisting of data signals from said data processing unit and data signals from said memory element means; encoder means coupled to said register means and to said memory element means for generating a group of error-correcting code (ECC) signals derived from said combination group of data signals, said group of code signals associated with said combination group of data signals; decoder means for locating an error in said group of data signals withdrawn from said memory element means, said error location determined by said group of memory data signals and said group of code signals associated with said group of memory data signals; first correction means coupled to said register means for correcting an error in said combination group of data signals based on said error location of said decoder means; second correction means coupled to said encoder means for correcting said group of code signals, said group of code signals derived from said combination group of data signals containing a signal at said error location, said corrected group of code signals associated with said corrected group of data signals, said corrected group of data signals and said associated corrected group of code signals stored in said memory element means; and apparatus, coupled to said register means, for by-passing said encoder and said decoder means, an error in a group of data signals being established by accompanying parity signals.

Claim 3

The memory module of claim 1 wherein said encoder means generates said group of code signals substantially simultaneously with said locating of an error by said decoding means.

Claim 4

In combination with a data processing unit, an improved memory module, said memory module having memory element means and error-correcting code (ECC) apparatus, wherein said ECC signals are provided with data signal groups for location of errors in said data signal groups, wherein the improvement comprises: first correction means for correcting a data signal group to be stored in said memory element means, said data signal group including an erroneous signal from said memory element means; second correction means for correcting ECC signals based on said data signal group including an erroneous signal from said memory element means; and decoder means for locating said erroneous signal from said memory element means, said locating of said erroneous signal occurring substantially simultaneously with generation of ECC signals for said data signal group.

Claim 5

In combination with a data processing unit, an improved memory module, said memory module having memory element means and error-correcting code (ECC) apparatus, wherein said ECC signals are provided with data signal groups for location of errors in said data signal groups, wherein the improvement comprises: first correction means for correcting a data signal group to be stored in said memory element means, said data signal group including an erroneous signal from said memory element means; second correction means for correcting ECC signals based on said data signal group including an erroneous signal from said memory element means; and decoder means for locating said erroneous signal from said memory element means, said locating of said erroneous signal occurring substantially simultaneously with generation of ECC signals for said data signal group.

Claim 8

In a memory module associated with a data processing unit, said memory module having memory element means for storage of data signals and error-correcting code (ECC) means, said ECC means including ECC encoder means for genErating ECC signals for a group of data signals, said group of data signals and said ECC signals stored in said memory module, said ECC means also including ECC decoder means for producing ECC syndrome bit signals for a one of said group of data signals and associated ECC signals extracted from said memory, said ECC syndrome bits locating an error in said group of data signals, said ECC means also including an ECC signal corrector apparatus comprising: register means for receiving a group of ECC signals from said ECC encoder means, said register means holding temporarily said group of ECC check bits, said register means coupled to said memory element means for storing of said group of ECC check bits; and syndrome decoder means coupled to said ECC decoder means and said register means for receiving a group of syndrome signals, said syndrome decoder means providing correction signals to said register means for correcting errors in said group of ECC signals, said register means delivering said corrected group of ECC signals for storing in said memory element means.

Claim 9

In a memory module associated with a data processing unit, said memory module having memory element means for storage of data signals and error-correcting code (ECC) means, said ECC means including ECC encoder means for genErating ECC signals for a group of data signals, said group of data signals and said ECC signals stored in said memory module, said ECC means also including ECC decoder means for producing ECC syndrome bit signals for a one of said group of data signals and associated ECC signals extracted from said memory, said ECC syndrome bits locating an error in said group of data signals, said ECC means also including an ECC signal corrector apparatus comprising: register means for receiving a group of ECC signals from said ECC encoder means, said register means holding temporarily said group of ECC check bits, said register means coupled to said memory element means for storing of said group of ECC check bits; and syndrome decoder means coupled to said ECC decoder means and said register means for receiving a group of syndrome signals, said syndrome decoder means providing correction signals to said register means for correcting errors in said group of ECC signals, said register means delivering said corrected group of ECC signals for storing in said memory element means.

Claim 10

In a memory module associated with a data processing unit, said memory module having memory element means for storage of data signals and error-correcting code (ECC) means, said ECC means including ECC encoder means for generating ECC signals for a group of data signals, said group of data signals and said ECC signals stored in said memory module, said ECC means also including ECC decoder means for producing ECC syndrome bit signals for a one of said group of data signals and associated ECC signals extracted from said memory, said ECC syndrome bits locating an error in said group of data signals, said ECC means also including an ECC signal corrector apparatus comprising: register means for receiving a group of ECC signals from said ECC encoder means, said register means holding temporarily said group of ECC check bits, said register means coupled to said memory element means for storing of said group of ECC check bits; and syndrome decoder means coupled to said ECC decoder means and said register means for receiving a group of syndrome signals, said syndrome decoder means providing correction signals to said register means for correcting errors in said group of ECC signals, said register means delivering said corrected group of ECC signals for storing in said memory element means, wherein said syndrome decoder means includes a first decoder means and a second decoder means, said first decoder means for comparing locations determined by syndrome signals with a location determined by data replacement signals from said data processing unit wherein a coincidence of said syndrome signals location and said data replacement location causes said first decoder means to apply a control signal to said second decoder means, said second decoder means for determining which of said ECC signals contain an error, said second decoder means generating said correction signals applied to said register means, said correction signals applied to said register means after receipt of said control signal from said first decoder means.

Claim 11

In a memory module associated with a data processing unit, said memory module having memory element means for storage of data signals and error-correcting code (ECC) means, said ECC means including ECC encoder means for generating ECC signals for a group of data signals, said group of data signals and said ECC signals stored in said memory module, said ECC means also including ECC decoder means for producing ECC syndrome bit signals for a one of said group of data signals and associated ECC signals extracted from said memory, said ECC syndrome bits locating an error in said group of data signals, said ECC means also including an ECC signal corrector apparatus comprising: register means for receiving a group of ECC signals from said ECC encoder means, said register means holding temporarily said group of ECC check bits, said register means coupled to said memory element means for storing of said group of ECC check bits; and syndrome decoder means coupled to said ECC decoder means and said register means for receiving a group of syndrome signals, said syndrome decoder means providing correction signals to said register means for correcting errors in said group of ECC signals, said register means delivering said corrected group of ECC signals for storing in said memory element means, wherein said syndrome decoder means includes a first decoder means and a second decoder means, said first decoder means for comparing locations determined by syndrome signals with a location determined by data replacement signals from said data processing unit wherein a coincidence of said syndrome signals location and said data replacement location causes said first decoder means to apply a control signal to said second decoder means, said second decoder means for determining which of said ECC signals contain an error, said second decoder means generating said correction signals applied to said register means, said correction signals applied to said register means after receipt of said control signal from said first decoder means.

Claim 12

In a memory module associated with a data processing unit, an improved method of performing a ''''partial-write'''' operation, said ''''partial-write'''' operation being a replacement of a portion of a group of data signals stored in said memory module by data signals from said data processing unit, said memory module including error-correction code ECC apparatus for location of an error generated in said stored group of data signals, wherein the improvement comprises: determining an error location in said group of memory data signals while substantially simultaneously generating ECC signals for a combination signal group including said group of memory data and said group of data processing unit data signals; and correcting said generated ECC signals and said combination signal group, said Error location establishing which of said ECC signals and which signal of said combination group of signals are to be corrected.

Claim 13

In a memory module associated with a data processing unit, an improved method of performing a ''''partial-write'''' operation, said ''''partial-write'''' operation being a replacement of a portion of a group of data signals stored in said memory module by data signals from said data processing unit, said memory module including error-correction code ECC apparatus for location of an error generated in said stored group of data signals, wherein the improvement comprises: determining an error location in said group of memory data signals while substantially simultaneously generating ECC signals for a combination signal group including said group of memory data and said group of data processing unit data signals; and correcting said generated ECC signals and said combination signal group, said Error location establishing which of said ECC signals and which signal of said combination group of signals are to be corrected.