Patent US3814919A successfully refreshed from Google Patents.
US3814919A
Expired / Lapsed
US
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Fault detection and isolation in a data processing system
Assignee: BAE Systems Defence Systems Ltd
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Filing: 1972-03-01
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Granted: 1974-06-04
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Expires: 1992-03-01
Abstract
Abstract A fault interrupt system is arranged, upon the detection of a fault to cause a processor in which the fault is detected to enter a fault check-out routine. Successive fault conditions detected while performing the fault check-out routine causes reentry into that routine. A faulty processor is therefore, trapped within the fault check-out routine. Additionally the detection of a fault causes the master capability register of the fault detecting processor to be overwritten with a capability defining a special capability table which is only relevant to the fault check-out programs. By this mechanism the faulty processor cannot, even under fault conditions, gain access to any storage areas outside those of the fault check-out programs. In the multi-processor/multi-storage module system of the PP250 a number of copies of the fault check-out programs and related workspace areas on a one copy per store module basis are provided together with a special capability pointer for each processor of the system and each entry into the check-out program is performed using a different store and therefore entry mechanism into the check-out programs copy so that intermittent processor faults or particular storage module faults will not maintain the processor indefinitely in the check-out program.
Inventors
- 👤 C Repton
- 👤 P Venton
- 👤 K Hodges
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:22
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0793; G06F11/0706; G06F11/0721; G06F11/0724; G06F11/073; G06F11/079; G06F11/16; G06F11/20; G06F11/202
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
284 words
A data processing system comprising, in combination, a memory means for providing storage in segmented form for information segments relative to application and supervisory programs and master and special capability tables, together with information segments relative to a fault check-out program; intercommunication means; and at least one processor module coupled through said intercommunication means to said memory means, each processor module cooperating with said memory means and provided with memory protection means comprising, a plurality of capability registers, means for loading said capability registers, each of said registers holding memory segment descriptor information indicative of the base and limit memory addresses of an information segment, a first of said capability registers being adapted to hold a first segment descriptor defining an information segment which contains a master capability table having an entry for each information segment in said memory means, in which is stored the base and limit memory addresses of the corresponding information segment, said master capability table providing the base and limit memory addresses of a descriptor when said loading means effects loading of one of the remaining capability registers, overwriting means for replacing information in said capability registers, and, fault detection and handling means for detecting a fault condition and in response to the fault condition to become immediately operative within the processor module to suspend the processor module from the active processing system by activating said overwriting means for replacing information in the master capability register of said processor module with special descriptor information defining a special capability table having entries for only those information segments in said memory which are relative to said fault check-out program alone to thereby condition said processor module to enter said fault check-out program.
Claim 2
Dependent Claim
284 words
A data processing system comprising, in combination, a memory means for providing storage in segmented form for information segments relative to application and supervisory programs and master and special capability tables, together with information segments relative to a fault check-out program; intercommunication means; and at least one processor module coupled through said intercommunication means to said memory means, each processor module cooperating with said memory means and provided with memory protection means comprising, a plurality of capability registers, means for loading said capability registers, each of said registers holding memory segment descriptor information indicative of the base and limit memory addresses of an information segment, a first of said capability registers being adapted to hold a first segment descriptor defining an information segment which contains a master capability table having an entry for each information segment in said memory means, in which is stored the base and limit memory addresses of the corresponding information segment, said master capability table providing the base and limit memory addresses of a descriptor when said loading means effects loading of one of the remaining capability registers, overwriting means for replacing information in said capability registers, and, fault detection and handling means for detecting a fault condition and in response to the fault condition to become immediately operative within the processor module to suspend the processor module from the active processing system by activating said overwriting means for replacing information in the master capability register of said processor module with special descriptor information defining a special capability table having entries for only those information segments in said memory which are relative to said fault check-out program alone to thereby condition said processor module to enter said fault check-out program.
Claim 3
Dependent Claim
176 words
A data processing system as claimed in claim 1, wherein said memory means comprises a plurality of storage modules accommodating a plurality of check-out program pointer segments in which the special descriptor information is stored, said check-out program pointer segments being distributed among the storage modules of said memory means on a mutually exclusive basis, said fault detection and handling means including first fault condition detection means for detecting a first fault condition, said memory protection means including check-out program pointer segment addressing means, said first fault condition detection means upon detecting a first fault condition activating said check-out program pointer segment addressing means to read said special descriptor from one of said check-out program pointer segments, said fault detection and handling means further including a further fault detection means for sensing the occurrence of the fault condition while said processor module is suspended from said active processing system and in response to such occurrence conditioning said check-out program pointer segment adDressing means to read said special descriptor from another of said check-out program pointer segments.
Claim 4
Dependent Claim
106 words
The data processing system as claimed in claim 2, wherein a plurality of copies of the information segments relative to said fault check-out program are provided in said memory means, said copies being distributed among said storage modules, each check-out pointer segment being arranged to hold (i) information relative to the area occupied by a different copy of said fault check-out program, and (ii) a pointer to the segment in which the instructions of said check-out program reside, each of said processor modules including means for loading one of said capability registers with the descriptor stored in the special capability table entry defined by said pointer.
Claim 5
Dependent Claim
56 words
The data processing system as claimed in claim 3 in which at least one processor module includes parity bit inversion means which are activated in response to the activation of said first fault condition detection means, to thereby invalidate all information in the processor module which is relative to programs other than said fault check-out programs.
Claim 6
Dependent Claim
60 words
A data processing system is claimed in claim 4 in which said first fault detection means includes a two-state switching device adapted to be switched to a first active state by the activation of said first fault condition detection means and to be switched to a second or inactive state in response to a particular instruction in said check-out program.
Claim 7
Dependent Claim
89 words
A data processing system as claimed in claim 5, and in which said two-state switching device when in said active state is adapted to cause the contents of a particular register in said check-out program pointer segment addressing means to be modified by a pre-determined amount each time said further fault condition detecting means is activated and said particular register is used to hold the address of said memory of the base address of the check-out program pointer segment to be used if a further fault condition is detected.
Claim 8
Dependent Claim
39 words
The data processing system as claimed in claim 6 wherein said at least one processor module includes means for replacing said first segment descriptor in said first master capability register upon the successful completion of said fault check-out program.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-03 | 1977-12-03 | 1978-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-03 | 1981-12-03 | 1982-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-03 | 1985-12-03 | 1986-06-04 | $7700.00 | Window Closed / Lapsed |