Patent US3812471A successfully refreshed from Google Patents.
US3812471A
Expired / Lapsed
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I/o device reserve system for a data processor
Assignee: Unisys Corp
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Filing: 1972-08-30
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Granted: 1974-05-21
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Expires: 1992-08-30
Abstract
Abstract An I/O device reserve function is provided for a data processing system in which any of a plurality of input-output (I/O) devices can be selectively reserved to any of a plurality of programs being executed by the system. A reserve register is located in each of the I/O devices to be reserved. On command from a program the reserve register of a selected device is loaded with a bit pattern which identifies the reserving program. The bit pattern stored in the reserve register of the device is compared with the bit pattern of any subsequent program attempting to reserve the same device. If the bit patterns are not identical the subsequent program receives a device ''''busy'''' signal indicating that the called device is reserved. A release circuit is provided for releasing the reserved device upon issuance of a release command thereto.
Inventors
- 👤 G Finnin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:35
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/161; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4022
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
360 words
In a data processing system having, a data processor section for executing one or more stored programs, a plurality of inputoutput devices, and an input-output control unit section which functions to transmit data and command signals received from the processor section to the input-output devices an improvement which comprises an input-output device reserve system for reserving any of said input-output devices to one or more programs being executed by said processor section wherein those of said programs desiring to reserve an input-output device contains a binary coded device reserve signal byte coded to identify the associated program, said reserve system comprising: a separate multi-bit reserve register for each of said inputoutput devices, separate read out means coupled to each of said reserve registers, means for activating a selected one of the read out means in response to a device selection signal received from said control unit section which selects the corresponding reserve register, an all zero detection circuit coupled to the output of the read out means of said reserve registers operative to produce an output when an all zero condition is read from the selected reserve register, a comparator, means coupling the output from the selected read out means of said reserve registers to said comparator as one input thereto, means coupling the coded device reserve signal byte received from the control unit to said comparator as a second input thereto whereby the contents being read from the selected reserve register are compared with the received coded device reserve signal byte, said comparator producing an output signal when the two inputs thereto correspond, means for storing the device reserve coded signal byte received from the control unit in the selected one of said reserve registers, said last named means being rendered active by a device reserve command signal received from said control unit in combination with an output from said all zero detection circuit, and signalling means responsive to the receipt of a reserve command signal from said control unit and to the outputs from either the all zero detection circuit or the comparator for indicating the reserve status of the input-output device corresponding to said selected reserve register.
Claim 2
Dependent Claim
360 words
In a data processing system having, a data processor section for executing one or more stored programs, a plurality of inputoutput devices, and an input-output control unit section which functions to transmit data and command signals received from the processor section to the input-output devices an improvement which comprises an input-output device reserve system for reserving any of said input-output devices to one or more programs being executed by said processor section wherein those of said programs desiring to reserve an input-output device contains a binary coded device reserve signal byte coded to identify the associated program, said reserve system comprising: a separate multi-bit reserve register for each of said inputoutput devices, separate read out means coupled to each of said reserve registers, means for activating a selected one of the read out means in response to a device selection signal received from said control unit section which selects the corresponding reserve register, an all zero detection circuit coupled to the output of the read out means of said reserve registers operative to produce an output when an all zero condition is read from the selected reserve register, a comparator, means coupling the output from the selected read out means of said reserve registers to said comparator as one input thereto, means coupling the coded device reserve signal byte received from the control unit to said comparator as a second input thereto whereby the contents being read from the selected reserve register are compared with the received coded device reserve signal byte, said comparator producing an output signal when the two inputs thereto correspond, means for storing the device reserve coded signal byte received from the control unit in the selected one of said reserve registers, said last named means being rendered active by a device reserve command signal received from said control unit in combination with an output from said all zero detection circuit, and signalling means responsive to the receipt of a reserve command signal from said control unit and to the outputs from either the all zero detection circuit or the comparator for indicating the reserve status of the input-output device corresponding to said selected reserve register.
Claim 3
Dependent Claim
36 words
The system as set forth in claim 1 wherein there is included, means for clearing a selected reserve register to an all zero condition in response to a release command signal received from the control unit.
Claim 4
Dependent Claim
278 words
In a data processing system having, a data processor section for executing one or more stored programs, a plurality of input-output devices, and an input-output control unit section which functions to transmit data and command signals received from the processor section to the input-output devices; an improvement which comprises an input-output device reserve system for reserving any of said input-output devices to one or more programs being executed by said processor section wherein those of said programs desiring to reserve an input-output device contains a binary coded device reserve signal byte coded to identify the associated program, said reserve system comprising: a separate multi-bit reserve register for each of said input-output devices, separate read out means coupled to each of said reserve registers, means for activating a selected one of the read out means in response to a device selection signal received from said control unit section which selects the corresponding reserve register, an all zero direction circuit coupled to the output of the read out means of said reserve registers operative to produce an output when an all zero condition is read out from the selected reserve register, means for storing the device reserve signal byte received from the control unit in said selected reserve register, said last named means being rendered operative by a device reserve command signal received from the control unit in combination with an output from the all zero detection circuit, and signalling means responsive to an output signal from the all zero detection circuit and to the receipt of a reserve command signal from the control unit for indicating the reserve status of the input-output devIce corresponding to said selected reserve register.
Claim 5
Dependent Claim
278 words
In a data processing system having, a data processor section for executing one or more stored programs, a plurality of input-output devices, and an input-output control unit section which functions to transmit data and command signals received from the processor section to the input-output devices; an improvement which comprises an input-output device reserve system for reserving any of said input-output devices to one or more programs being executed by said processor section wherein those of said programs desiring to reserve an input-output device contains a binary coded device reserve signal byte coded to identify the associated program, said reserve system comprising: a separate multi-bit reserve register for each of said input-output devices, separate read out means coupled to each of said reserve registers, means for activating a selected one of the read out means in response to a device selection signal received from said control unit section which selects the corresponding reserve register, an all zero direction circuit coupled to the output of the read out means of said reserve registers operative to produce an output when an all zero condition is read out from the selected reserve register, means for storing the device reserve signal byte received from the control unit in said selected reserve register, said last named means being rendered operative by a device reserve command signal received from the control unit in combination with an output from the all zero detection circuit, and signalling means responsive to an output signal from the all zero detection circuit and to the receipt of a reserve command signal from the control unit for indicating the reserve status of the input-output devIce corresponding to said selected reserve register.
Claim 6
Dependent Claim
36 words
The combination set forth in claim 3 wherein there is further included means for clearing the selected reserve register to an all zero condition in response to a release command signal received from the control units.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-05-20 | 1977-11-19 | 1978-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-05-20 | 1981-11-19 | 1982-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-05-20 | 1985-11-19 | 1986-05-21 | $7700.00 | Window Closed / Lapsed |