Abstract A hybrid master/slave device latch including a dynamic input stage is operable under a two-phase clock and set and reset inputs to set or reset a static output stage. If a latch is implemented in MOSFET logic to operate in the purely dynamic mode and the latch is not refreshed at, for instance, the rate of 10 kHz, a malfunction may occur due to the leakage of charges from temporary storage capacitors. With this dynamic type of latch, due to the relatively high refresh frequencies required, extreme difficulty is encountered in testing. While a static type of device can be operated at extremely low or zero frequencies and thus can be readily tested, it requires more MOSFET devices. The subject invention combines the attributes of the fewer number of components required in a dynamic latch with the memory ability of a static latch in a particular implementation such that there are fewer MOSFET devices required than would be required in either a purely static or dynamic latch.
A two-phase master/slave device for providing set or reset outputs at phase two time at an output stage depending on whether a set or reset input is applied to the input stage of the device at phase one time comprising: a. a dynamic input stage responsive to a phase one clock pulse including a temporary set storage means and a temporary reset storage means and means for charging one of said storage means in accordance with whether a set or reset input is applied to said stage, b. a static output stage which is set into a set or reset condition depending on the conditioning of said dynamic stage, and c. a switching means responsive to a phase two clock pulse for applying the conditioning of said dynamic stage to said static output stage.
Claim 2
Dependent Claim
134 words
A two-phase master/slave device for providing set or reset outputs at phase two time at an output stage depending on whether a set or reset input is applied to the input stage of the device at phase one time comprising: a. a dynamic input stage responsive to a phase one clock pulse including a temporary set storage means and a temporary reset storage means and means for charging one of said storage means in accordance with whether a set or reset input is applied to said stage, b. a static output stage which is set into a set or reset condition depending on the conditioning of said dynamic stage, and c. a switching means responsive to a phase two clock pulse for applying the conditioning of said dynamic stage to said static output stage.
Claim 3
Dependent Claim
22 words
The master/slave device of claim 1 further wherein said temporary storage means are the inherent stray capacitance in said dynamic input stage.
Claim 4
Dependent Claim
14 words
The master/slave device of claim 1 further wherein said temporary storage means are capacitors.
Claim 5
Dependent Claim
44 words
The master/slave device of claim 3 further wherein said set and reset signals do not overlap and are gated to charge their said associated temporary storage capacitors by application of a signal at phase one time to associated set and reset field effect transistors.