Control command security in binary remote control

Claim 3

a data pulse is received during each period.

Claim 4

a data pulse is received during each period.

Claim 5

The method of claim 1, further characterized by: D. in each group of data pulses transmitting one data pulse which has a substantially different duration than the other data pulses of the group and which one data pulse is always in the same position in the group; and E. utilizing for control only received control commands in which, further, the data pulse in said position in the group is of substantially said different duration.

Claim 6

a counting input connected with the clock oscillator for counting clock pulses, and

Claim 7

a counting input connected with the clock oscillator for counting clock pulses, and

Claim 8

having a control input upon which it can receive pulse signals, by each of which it is set to zero, and

Claim 9

having a control input upon which it can receive pulse signals, by each of which it is set to zero, and

Claim 10

having a control input upon which it can receive pulse signals, by each of which it is reset to zero, and

Claim 11

having a control input upon which it can receive pulse signals, by each of which it is reset to zero, and

Claim 12

a control input connected with said means for producing a control signal and whereby the pause duration counter means is caused to count clock pulses when the control signal has said other signification and is reset to zero promptly upon said control signal having said one signification, and

Claim 13

a control input connected with said means for producing a control signal and whereby the pause duration counter means is caused to count clock pulses when the control signal has said other signification and is reset to zero promptly upon said control signal having said one signification, and

Claim 14

an output upon which an ''''overlength pause'''' pulse signal appears when the pause duration counter means has counted a number of clock pulses which is in excess of that corresponding to said predetermined pause duration; and H. logic connection means between the output of the pause duration counter meanS and the gate means whereby the gate means is prevented from transferring from the shift register to the control command utilization means a control command that gives rise to an ''''overlength pause'''' signal on the output of the pause duration counter means, notwithstanding the concurrent existence of other signals that tend to effect such transfer.

Claim 15

an output upon which an ''''overlength pause'''' pulse signal appears when the pause duration counter means has counted a number of clock pulses which is in excess of that corresponding to said predetermined pause duration; and H. logic connection means between the output of the pause duration counter meanS and the gate means whereby the gate means is prevented from transferring from the shift register to the control command utilization means a control command that gives rise to an ''''overlength pause'''' signal on the output of the pause duration counter means, notwithstanding the concurrent existence of other signals that tend to effect such transfer.

Claim 16

an output upon which an ''''accept bit'''' pulse signal appears when a number of clock pulses corresponding to said predetermined pulse duration has been counted; D. a shift register having a control input connected with said output of said counter means and which is arranged to accept each data pulse upon its receipt provided a concurrent ''''accept bit'''' signal has appeared upon the output of said counter means; E. second counter means having a counting input connected with the output of the data pulse duration counter means and which issues an ''''accept command'''' pulse signal each time it has counted a number of ''''accept bit'''' pulse signals equal to the number of data pulses in a normal control command; and F. gate means connected with the shift register and with control command utilization apparatus, said gate means having a control input which is connected with the second counter means and being arranged to transfer shift register contents to said control command utilization apparatus in consequence of an ''''accept command'''' pulse signal.

Claim 17

an output upon which an ''''accept bit'''' pulse signal appears when a number of clock pulses corresponding to said predetermined pulse duration has been counted; D. a shift register having a control input connected with said output of said counter means and which is arranged to accept each data pulse upon its receipt provided a concurrent ''''accept bit'''' signal has appeared upon the output of said counter means; E. second counter means having a counting input connected with the output of the data pulse duration counter means and which issues an ''''accept command'''' pulse signal each time it has counted a number of ''''accept bit'''' pulse signals equal to the number of data pulses in a normal control command; and F. gate means connected with the shift register and with control command utilization apparatus, said gate means having a control input which is connected with the second counter means and being arranged to transfer shift register contents to said control command utilization apparatus in consequence of an ''''accept command'''' pulse signal.

Claim 18

having an output upon which it imposes an output signal when it has counted a predetermined number of ''''accept command'''' pulse signals; J. means connecting the control input of said acceptable command counter means with the output of the pause duration counter means, to cause each ''''overlength pause'''' signal to reset the acceptable command counter means to zero; and K. logic means connecting the output of the acceptable command counter means with said gate means and arranged to cause the gate means to effect transfer of a control command from the shift register to the control command utilization means in response to an ''''accept command'''' pulse signal only if the same is issued substantially concurrently with the presence of said output signal on the output of the acceptable command counter means, so that the gate means cannot effect such transfer until the last said predetermined number of successive ''''accept command'''' signals has been issued, signifying that at least that number of successive uncorrupted control commands has been received.

Claim 19

having an output upon which it imposes an output signal when it has counted a predetermined number of ''''accept command'''' pulse signals; J. means connecting the control input of said acceptable command counter means with the output of the pause duration counter means, to cause each ''''overlength pause'''' signal to reset the acceptable command counter means to zero; and K. logic means connecting the output of the acceptable command counter means with said gate means and arranged to cause the gate means to effect transfer of a control command from the shift register to the control command utilization means in response to an ''''accept command'''' pulse signal only if the same is issued substantially concurrently with the presence of said output signal on the output of the acceptable command counter means, so that the gate means cannot effect such transfer until the last said predetermined number of successive ''''accept command'''' signals has been issued, signifying that at least that number of successive uncorrupted control commands has been received.

Claim 20

having an output upon which it imposes an output signal when it has counted a predetermined number of ''''accept command'''' pulse signals; J. means connecting the control input of said acceptable command counter means with the output of the logic connection means, to cause the acceptable command counter means to go to zero each time it receives one of said inhibiting signals; and K. logic means connecting the output of the acceptable command counter means with said gate means and arranged to cause the gate means to transfer a control command from the shift register to the utilization means in response to an ''''accept command'''' pulse signal only if the same is issued substantially concurrently with the presence of said output signal on the output of the acceptable commaNd counter means, so that the gate means cannot effect such transfer until the last of said predetermined number of successive ''''accept command'''' signals has been issued, signifying that at least that number of successive uncorrupted control commands has been received.

Claim 21

having an output upon which it imposes an output signal when it has counted a predetermined number of ''''accept command'''' pulse signals; J. means connecting the control input of said acceptable command counter means with the output of the logic connection means, to cause the acceptable command counter means to go to zero each time it receives one of said inhibiting signals; and K. logic means connecting the output of the acceptable command counter means with said gate means and arranged to cause the gate means to transfer a control command from the shift register to the utilization means in response to an ''''accept command'''' pulse signal only if the same is issued substantially concurrently with the presence of said output signal on the output of the acceptable commaNd counter means, so that the gate means cannot effect such transfer until the last of said predetermined number of successive ''''accept command'''' signals has been issued, signifying that at least that number of successive uncorrupted control commands has been received.

Claim 22

The method of claim 1, further characterized by: D. during each pause between received Data pulses counting clock pulses; and E. utilizing for control only received control commands in which, further, no pause between successive received data pulses of a group exceeds in duration the time required to generate a predetermined number of clock pulses.

Claim 23

The method of claim 1, further characterized by: D. converting each received data pulse to a data bit; E. temporarily storing a number of data bits equal to the data pulses in a complete control command; and F. utilizing each received control command for control only if its immediately preceding control command has been found qualified to be utilized for control.

Claim 24

In remote control apparatus wherein control commands are transmitted and received in the form of binary data pulses, every control command comprising the same number of data pulses as every other, and every data pulse of a control command normally having at least a predetermined pulse duration and being normally defined from the next succeeding data pulse by a pause of not in excess of a predetermined pause duration, means for preventing control commands that are received in corrupted form from being utilized to effect responses, said means comprising: A. means responsive to control commands as the same are received for producing a control signal which has one binary signification during receipt of a data pulse and the opposite binary signification during a pause between received data pulses; B. a clock oscillator for producing clock pulses at a frequency substantially higher than the normal frequency of data pulses in a control command; C. data pulse duration counter means having

Claim 25

In remote control apparatus wherein control commands are transmitted and received in the form of binary data pulses, every control command comprising the same number of data pulses as every other, and every data pulse of a control command normally having at least a predetermined pulse duration and being normally defined from the next succeeding data pulse by a pause of not in excess of a predetermined pause duration, means for preventing control commands that are received in corrupted form from being utilized to effect responses, said means comprising: A. means responsive to control commands as the same are received for producing a control signal which has one binary signification during receipt of a data pulse and the opposite binary signification during a pause between received data pulses; B. a clock oscillator for producing clock pulses at a frequency substantially higher than the normal frequency of data pulses in a control command; C. data pulse duration counter means having

Claim 26

The remote control apparatus of claim 5, further characterized by: G. pause duration counter means having

Claim 27

The remote control apparatus of claim 5 wherein the last data pulse of every control command has a longer predetermined duration than the other data pulses thereof, further characterized by: G. said data pulse duration counter means having a second output upon which a ''''last bit'''' pulse signal appears when the data pulse duration counter means has counted a number of clock pulses corresponding to said longer predetermined duration; and H. logic connection means connecting said second output of the data pulse duration counter means with the output of said second counter means and with the control input of the gate means, and arranged to produce an inhibiting signal that prevents the gate means from transferring from the shift register to the control command utilization means a control command that does not give rise to a ''''last bit'''' pulse signal substantially concurrently with an ''''accept command'''' pulse signal.

Claim 28

The remote control apparatus of claim 6, further characterized by: I. acceptable command counter means

Claim 29

The remote control apparatus of claim 7, further characterized by: I. acceptable command counter means