Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
813 words
A PCM voice-frequency telecommunication system with a first station and a second station linked with each other by a signal path for the transmission, in a recurrent message frame, of digitized message samples in the form of multibit pulse codes between groups of local voice channels served by said first station and groups of local voice channels served by said second station, comprising: synchronized timing means at said first and second stations establishing recurrent frames and subframes; a group coder for each group of a voice channels at said first station generating during each frame a continuous code sequence extending over n sampling intervals and containing blank codes relating to inactive channels along with code words representing the digitized message samples of all active channels of its group in a predetermined order; monitoring means at said first station for determining the activity of all in channels of a group; first processing means at said first station responsive to an activity pattern from said monitoring means for eliminating all blank codes from said continuous code sequence issuing from the corresponding group coder and consolidating the remaining code words thereof into code groupings forming part of an intermittent code sequence, each code grouping containing a maximum number of bits equaling the number of time slots allotted to the channel group in an assigned subframe within each message frame; multiplexing means at said first station connected to said processing means for delivering said intermittent code sequence to said signal path in its assigned subframe and in interleaved relationship with similar code sequences from other channel groups; first storage means individual to a channel group at said first station including a first n-stage input memory connected to said monitoring means for registering said activity pattern and a first n-stage output memory connected to said first processing means for controlling the elimination of said blank codes, said activity pattern including a characteristic bit for each active channel; first cyclic scanning means at said first station connected to be periodically stepped by said timing means for controlling the stage-by-stage transfer, during each frame, of said activity pattern from said first input memory to said first output memory with generation of a first output pulse upon the transfer of each characteristic bit; first counting means at said first station connected to receive said first output pulses from said first scanning means and to arrest same upon rEaching, in any frame, a predetermined maximum pulse count determined by the number of time slots allotted to the corresponding channel group, said first counting means being resettable by said timing means for restarting the pulse count in each frame with resumption of transfer of the activity pattern from said first input memory to said first output memory at a randomly selected stage of said first input and output memories; demultiplexing means at said second station connected to said signal path for recovering said intermittant code sequence from arriving message signals; second processing means at said second station connected to said demultiplexing means for receiving said intermittent code sequence therefrom and reconverting same into a continuous code sequence with interspersed blank codes relating to inactive channels; insertion means in said first processing means connected to said monitoring means for introducing an aliquot q-bit fraction of an n-bit allocation message, corresponding to said activity pattern, into each of said code groupings with transmission of a complete allocation message in the course of a predetermined frame series; retrieval means at said second station connected to extract said q-bit fraction from said demultiplexing means for reconstituting said allocation message therefrom; second storage means individual to a channel group at said second station including a second n-stage input memory connected to said retrieval means for registering a replica of said activity pattern and a second n-stage output memory connected to said second processing means for determining the time position of the individual code words of said intermittent code sequence in the continuous code sequence issuing from said second processing means; second cyclic scanning means at said second station connected to be periodically stepped by said timing means for controlling the stage-by-stage transfer, during each frame, of said replica from said second input memory to said second output memory with generation of a second output pulse upon the transfer of each characteristic bit; second counting means at said second station connected to receive said second output pulses from said second scanning means and to arrest same upon reaching, in any frame, said predetermined maximum pulse count, said second counting means being resettable by said timing means for restarting the pulse count in each frame with resumption of transfer of said replica from said second input memory to said second output memory at a stage of said second input and output memories corresponding to said randomly selected stage; and decoding means for said code words connected to said processing means.
Claim 2
Dependent Claim
813 words
A PCM voice-frequency telecommunication system with a first station and a second station linked with each other by a signal path for the transmission, in a recurrent message frame, of digitized message samples in the form of multibit pulse codes between groups of local voice channels served by said first station and groups of local voice channels served by said second station, comprising: synchronized timing means at said first and second stations establishing recurrent frames and subframes; a group coder for each group of a voice channels at said first station generating during each frame a continuous code sequence extending over n sampling intervals and containing blank codes relating to inactive channels along with code words representing the digitized message samples of all active channels of its group in a predetermined order; monitoring means at said first station for determining the activity of all in channels of a group; first processing means at said first station responsive to an activity pattern from said monitoring means for eliminating all blank codes from said continuous code sequence issuing from the corresponding group coder and consolidating the remaining code words thereof into code groupings forming part of an intermittent code sequence, each code grouping containing a maximum number of bits equaling the number of time slots allotted to the channel group in an assigned subframe within each message frame; multiplexing means at said first station connected to said processing means for delivering said intermittent code sequence to said signal path in its assigned subframe and in interleaved relationship with similar code sequences from other channel groups; first storage means individual to a channel group at said first station including a first n-stage input memory connected to said monitoring means for registering said activity pattern and a first n-stage output memory connected to said first processing means for controlling the elimination of said blank codes, said activity pattern including a characteristic bit for each active channel; first cyclic scanning means at said first station connected to be periodically stepped by said timing means for controlling the stage-by-stage transfer, during each frame, of said activity pattern from said first input memory to said first output memory with generation of a first output pulse upon the transfer of each characteristic bit; first counting means at said first station connected to receive said first output pulses from said first scanning means and to arrest same upon rEaching, in any frame, a predetermined maximum pulse count determined by the number of time slots allotted to the corresponding channel group, said first counting means being resettable by said timing means for restarting the pulse count in each frame with resumption of transfer of the activity pattern from said first input memory to said first output memory at a randomly selected stage of said first input and output memories; demultiplexing means at said second station connected to said signal path for recovering said intermittant code sequence from arriving message signals; second processing means at said second station connected to said demultiplexing means for receiving said intermittent code sequence therefrom and reconverting same into a continuous code sequence with interspersed blank codes relating to inactive channels; insertion means in said first processing means connected to said monitoring means for introducing an aliquot q-bit fraction of an n-bit allocation message, corresponding to said activity pattern, into each of said code groupings with transmission of a complete allocation message in the course of a predetermined frame series; retrieval means at said second station connected to extract said q-bit fraction from said demultiplexing means for reconstituting said allocation message therefrom; second storage means individual to a channel group at said second station including a second n-stage input memory connected to said retrieval means for registering a replica of said activity pattern and a second n-stage output memory connected to said second processing means for determining the time position of the individual code words of said intermittent code sequence in the continuous code sequence issuing from said second processing means; second cyclic scanning means at said second station connected to be periodically stepped by said timing means for controlling the stage-by-stage transfer, during each frame, of said replica from said second input memory to said second output memory with generation of a second output pulse upon the transfer of each characteristic bit; second counting means at said second station connected to receive said second output pulses from said second scanning means and to arrest same upon reaching, in any frame, said predetermined maximum pulse count, said second counting means being resettable by said timing means for restarting the pulse count in each frame with resumption of transfer of said replica from said second input memory to said second output memory at a stage of said second input and output memories corresponding to said randomly selected stage; and decoding means for said code words connected to said processing means.
Claim 3
Dependent Claim
44 words
A system as defined in claim 1 wherein said first and second scanning means are provided with synchronized resetting means controlled by said timing means for restoration to a starting position after a period equaling a whole number of times said predetermined frame series.
Claim 4
Dependent Claim
65 words
A system as defined in claim 1 wherein said monitoring means is controlled by said timing means to update the contents of said first input memory during a succession of p consecutive frames, p being an integer greater than 1, said predetermined frame series encompassing np/q frames, said retrieval means including logical circuity for evaluating said q-bit fraction during corresponding successions of p consecutive frames.
Claim 5
Dependent Claim
46 words
A system as defined in claim 3, further comprising synchronization means at said first station controlled by said timing means for insertion of a synchronizing bit into each of said code grouping once every p frames, said retrieval means including detector means for said synchronizing bit.
Claim 6
Dependent Claim
48 words
A system as defined in claim 3 wherein said first and second counting means each comprises a ring counter, a source of stepping pulses for said ring counter in said timing means, and blocking means for said stepping pulSes controlled by said first and second counting means, respectively.
Claim 7
Dependent Claim
50 words
A system as defined in claim 5 wherein said first and second counting means each comprises a linear pulse counter, digital signaling means set to convey a set of reference bits representing said maximum pulse count, and comparison means connected to said linear pulse counter and to said signaling means.
Claim 8
Dependent Claim
31 words
A system as defined in claim 1 wherein said first processing means comprises a pair of shift registers alternately controlled by said timing means for loading and unloading in respective frames.
Claim 9
Dependent Claim
31 words
A system as defined in claim 1 wherein said second processing means comprises a pair of random-access memories alternately controlled by said timing means for loading and unloading in respective frames.
Claim 10
Dependent Claim
49 words
A system as defined in claim 1 wherein the stages of said first input memory are divided into m sets of q stages each, with m.q n, said insertion means being successively connectable to the stage outputs of each of said m sets for deriving said q-bit fraction therefrom.
Claim 11
Dependent Claim
62 words
A system as defined in claim 1 wherein each of said storage means comprises an n-stage operating memory inserted between the associated output memory and processing means, said operating memory being provided with enabling inputs connected to said timing means for updating the contents of its n stages once per frame from the contents of corresponding stages of the associated output memory.