Apparatus to detect phase encoded data being read from a data storage subsystem

Claim 2

Apparatus for detecting a data envelope having a predetermined number of preamble pulses followed by a plurality of data pulses, for use with a source of pulses and a source of timing signals, said apparatus including: first and second up/down counters each having first and second input leads and first, second and third output leads, said first input of said second counter being connected to said second output lead of said first counter, said second input lead of said second counter being connected to said third output lead of said first counter; first means for developing a voltage from pulses, said first means for developing being connected to said source of pulses, said first means for developing being coupled to said second input lead of said first counter; second means for developing a voltage from signals, said second means for developing being connected to said source of timing signals, said second means for developing being coupled to said first input lead of said first counter; first and second gating means, said first gating means being connected between said source of pulses and said first input lead of said counter, said second gating means being connected between said source of signals and said second input lead of said first counter; and a logic gate having an output lead and first, second and third input leads, said first output lead of said first counter being connected to a first input lead of said logic gate, said first and said second output leads of said second counter each being connected to a corresponding one of said input leads of said logic gate.

Claim 3

Apparatus for detecting a data envelope as defined in claim 1 including: a latching circuit having first and second input leads and an output lead, said first input lead of said latching circuit bieng connected to said output lead of said logic gate, said second input lead of said latching circuit being coupled to said second output lead of said second counter.

Claim 4

Apparatus for detecting a data envelope having a predetermined number of preamble pulses followed by a plurality of data pulses, for use with a source of pulses and a source of timng signals, said apparatus comprising: first and second up/down counters each having first and second input leads and first, second and third output leads, said first input lead of said second counter being connected to said second output lead of said first counter, said second input lead of said second counter being connected to said third output lead of said first counter; first, second, third and fourth flip-flops each having an output lead, a reset lead and first, second and third input leads, said second input leads of said first and said second flip-flops being coupled to said source of signals, said second input leads of said third and said fourth flip-flops being coupled to said source of pulses, said source of pulses being coupled to said reset leads of said first and said second flip-flops, said output lead of said first flip-flop being connected to said first input lead of said second flip-flop, said output lead of said third flip-flop being connected to said first input lead of said fourth flip-flop; first and second reference potentials, said first potential being connected to said first input leads of said first and said third flip-flops, said second potential being connected to said third input leads of said second and said fourth flip-flops; first, second and third logic gates each having first, second and third input leads and an output lead, said output lead of said second gate being connected to said first input lead of said first counter, said output lead of said third gate being connected to said second input lead of said first counter, said second input lead of said third logic gate being connected to said source of signals, said first input lead of said second logic gate being connected to said output lead of said first logic gate, said first output lead of said first counter being connected to said first input lead of said first logic gate, said first output lead of said second counter being connected to said second input lead of said first logic gate, said second output lead of said second counter being coupled to said third input lead of said first logic gate; and first and second gating means each having first and second input leads and an output lead, said output lead of said first gating means being coupled to said third input lead of said first flip-flop and to said first input lead of said third logic gate, said first input lead of said first gating means being connected to said output lead of said first flip-flop, said second input lead of said first gating means being connected to said output lead of said second flip-flop, said output lead of said first gating means being connected to said output lead of said second flip-flop, said output lead of said first gating means being connected to said reset leads of said third and said fourth flip-flops, said first input lead of said second gating means being connected to said output lead of said third flip-flop, said second input lead of said second gating means being connected to said output lead of said fourth flip-flop, said output lead of said second gating means being coupled to said third input lead of said third of said flip-flop and to said second input lead of said second logic gate.

Claim 5

Apparatus for detecting a data envelope having a predetermined number of preamble pulses followed by a plurality of data pulses, for use with a source of pulses and a source of timng signals, said apparatus comprising: first and second up/down counters each having first and second input leads and first, second and third output leads, said first input lead of said second counter being connected to said second output lead of said first counter, said second input lead of said second counter being connected to said third output lead of said first counter; first, second, third and fourth flip-flops each having an output lead, a reset lead and first, second and third input leads, said second input leads of said first and said second flip-flops being coupled to said source of signals, said second input leads of said third and said fourth flip-flops being coupled to said source of pulses, said source of pulses being coupled to said reset leads of said first and said second flip-flops, said output lead of said first flip-flop being connected to said first input lead of said second flip-flop, said output lead of said third flip-flop being connected to said first input lead of said fourth flip-flop; first and second reference potentials, said first potential being connected to said first input leads of said first and said third flip-flops, said second potential being connected to said third input leads of said second and said fourth flip-flops; first, second and third logic gates each having first, second and third input leads and an output lead, said output lead of said second gate being connected to said first input lead of said first counter, said output lead of said third gate being connected to said second input lead of said first counter, said second input lead of said third logic gate being connected to said source of signals, said first input lead of said second logic gate being connected to said output lead of said first logic gate, said first output lead of said first counter being connected to said first input lead of said first logic gate, said first output lead of said second counter being connected to said second input lead of said first logic gate, said second output lead of said second counter being coupled to said third input lead of said first logic gate; and first and second gating means each having first and second input leads and an output lead, said output lead of said first gating means being coupled to said third input lead of said first flip-flop and to said first input lead of said third logic gate, said first input lead of said first gating means being connected to said output lead of said first flip-flop, said second input lead of said first gating means being connected to said output lead of said second flip-flop, said output lead of said first gating means being connected to said output lead of said second flip-flop, said output lead of said first gating means being connected to said reset leads of said third and said fourth flip-flops, said first input lead of said second gating means being connected to said output lead of said third flip-flop, said second input lead of said second gating means being connected to said output lead of said fourth flip-flop, said output lead of said second gating means being coupled to said third input lead of said third of said flip-flop and to said second input lead of said second logic gate.

Claim 6

Apparatus for detecting a data envelope as defined in claim 3 including: a latching circuit for first and second input leads and an output lead, said first input lead of said latching circuit being connected to said output lead of said first logic gate, said second input lead of said latching circuit being coupled to said third input lead of said first logic gate.