Adaptive electronic hybrid transformer

Claim 2

In combination, signal supplying means, signal receiving means, load means, signal controlling means connected between said signal supplying means and said load means, summing means connected to receive signals from said signal supplying means and from said signal controlling means where connected to said load means, and controller means connected between said summing means and said signal controlling means in order to control the operation of said signal controller as a function of the signal produced by said summing means, and said summing means connected to said signal receiving means to supply signals thereto which signals are substantially independent of the signals supplied by said signal supplying means.

Claim 3

An adaptive electronic hybrid transformer circuit to be interposed between a transmitter and a receiver, at the same end of a transmission line over which signals are being simultaneously transmitted and received, said transformer circuit comprising, a transmitter terminal; a receiver terminal; a line terminal; summing means connected to said transmitter terminal and said line terminal for summing the signal applied at said line terminal from said transmission line with the transmitter signal applied at said transmitter terminal from said transmitter, said summing means connected to said receiver terminal for supplying a sum signal to said receiver, said signal from said transmission line including transmitter signal and receiver signal components; detecting means responsive to said sum signal supplied by said summing means for detecting changes in parameters of said transmitter signal component, said detecting means including first circuit means for receiving said sum signal and said transmitter signal from said transmitter at said transmitter terminal in order to correlate the amplitude of the transmitter signal component in said sum signal supplied by said summing means with the amplitude of said transmitter signal from the transmitter and to generate an output signal representing the amplitude difference between the signals supplied thereto, and second circuit means for receiving said sum signal from said summing means and a signal representative of said transmitter signal from said transmitter in order to correlate the phase of said transmitter signal component in said sum signal supplied by said summing means with said transmitter signal and to generate an output signal representing the phase difference between said transmitter signal and said transmitter signal component in said transmission line signal; phase shift means; and gaIn control means; said phase shift means and said gain control means connected between said transmitter terminal and said line terminal, said first circuit means of said detecting means connected to said gain control means to control the operation thereof, said second circuit means of said detecting means connected to said phase shift means to control the operation thereof, whereby said phase shift means and said gain control means cause changes in the phase and amplitude of said transmitter signal component in the transmission line signal until said sum signal from said summing means represents the receiver signal component only.

Claim 4

An adaptive electronic hybrid transformer circuit to be interposed between a transmitter and a receiver, at the same end of a transmission line over which signals are being simultaneously transmitted and received, said transformer circuit comprising, a transmitter terminal; a receiver terminal; a line terminal; summing means connected to said transmitter terminal and said line terminal for summing the signal applied at said line terminal from said transmission line with the transmitter signal applied at said transmitter terminal from said transmitter, said summing means connected to said receiver terminal for supplying a sum signal to said receiver, said signal from said transmission line including transmitter signal and receiver signal components; detecting means responsive to said sum signal supplied by said summing means for detecting changes in parameters of said transmitter signal component, said detecting means including first circuit means for receiving said sum signal and said transmitter signal from said transmitter at said transmitter terminal in order to correlate the amplitude of the transmitter signal component in said sum signal supplied by said summing means with the amplitude of said transmitter signal from the transmitter and to generate an output signal representing the amplitude difference between the signals supplied thereto, and second circuit means for receiving said sum signal from said summing means and a signal representative of said transmitter signal from said transmitter in order to correlate the phase of said transmitter signal component in said sum signal supplied by said summing means with said transmitter signal and to generate an output signal representing the phase difference between said transmitter signal and said transmitter signal component in said transmission line signal; phase shift means; and gaIn control means; said phase shift means and said gain control means connected between said transmitter terminal and said line terminal, said first circuit means of said detecting means connected to said gain control means to control the operation thereof, said second circuit means of said detecting means connected to said phase shift means to control the operation thereof, whereby said phase shift means and said gain control means cause changes in the phase and amplitude of said transmitter signal component in the transmission line signal until said sum signal from said summing means represents the receiver signal component only.

Claim 5

The circuit recited in claim 2 wherein said gain control means includes amplifier means having at least an output terminal and an input terminal, and variable impedance means connected in a feedback path from an output terminal to a terminal of said amplifier, said variable impedance means coupled to and controlled by said first circuit means of said detecting means.

Claim 6

The circuit recited in claim 2 wherein said phase shift means includes amplifier means, and variable impedance means connected in series with said amplifier means, said variable impedance means connected to and controlled by said second circuit means of said detecting means.

Claim 7

The circuit recited in claim 2 wherein each of said first and second circuit means of said detecting means includes a pair of semiconductor devices having the conduction paths thereof connected in series, amplifier means having at least an input terminal and an output terminal, the input terminals of said amplifier means connected to receive said transmitter signal or said signal representative of said transmitter signal, the control electrodes of one of said semiconductor devices connected to the output terminal of said amplifier means, inverter means connected between said output terminal and the control electrode of the other one of said semiconductor devices, means for supplying said sum signal from said summing means and the inverse thereof to the opposite ends of the series connected conduction path of said semiconductor devices, and integrator means having the input terminal thereof connected to a common circuit point with said series connected conduction paths of said semiconductor devices, the output terminal of said integrator means connected to one of said phase shift means and said gain control means.

Claim 8

The circuit recited in claim 5 wherein said amplifier means are inverting type amplifiers, and said semiconductor devices are field effect transistors.

Claim 9

The circuit recited in claim 2 wherein said phase shift means and said gain control means adjust the phase and amplitude of the transmitter signal by an amount approximately equal and opposite to the phase and amplitude changes introduced into the transmitter signal by the complex impedance features of the transmission line.

Claim 10

The circuit recited in claim 2 including a phase shift circuit between said transmitter and said second circuit means for shifting the phase of said transmitter signal by approximately 90*.

Claim 11

The circuit recited in claim 8 wherein said first and second circuit means include first and second integrator circuit means respectively, said first integrator circuit means providing an output signal according to the expression