Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
193 words
Character generating apparatus for controlling the deflection control circuits of a cathode ray tube to move an electron beam across the screen of said cathode ray tube to display a character thereon, said character being formed of a plurality of straight line segments, said apparatus comprising means for receiving a character code and transforming said character code into an address code, memory means responsive to said address code for sequentially providing words each containing a horizontal and vertical deflection increment and beam control signals for a line segment of said character, logic means for converting said horizontal and vertical deflection increment signals in each of said words into respective binary bit streams each having as many 1''s as the length of the respective coordinate component of the line segment, said logic means comprising binary to unitary converting means for converting a binary representation of a number into a binary word having an amount of 1''s equal to said number, said binary to unitary converter including means for packing said 1''s at one end of said binary word, and means for converting said bit streams into stroke signals for application to said deflection circuits.
Claim 2
Dependent Claim
193 words
Character generating apparatus for controlling the deflection control circuits of a cathode ray tube to move an electron beam across the screen of said cathode ray tube to display a character thereon, said character being formed of a plurality of straight line segments, said apparatus comprising means for receiving a character code and transforming said character code into an address code, memory means responsive to said address code for sequentially providing words each containing a horizontal and vertical deflection increment and beam control signals for a line segment of said character, logic means for converting said horizontal and vertical deflection increment signals in each of said words into respective binary bit streams each having as many 1''s as the length of the respective coordinate component of the line segment, said logic means comprising binary to unitary converting means for converting a binary representation of a number into a binary word having an amount of 1''s equal to said number, said binary to unitary converter including means for packing said 1''s at one end of said binary word, and means for converting said bit streams into stroke signals for application to said deflection circuits.
Claim 3
Dependent Claim
61 words
The apparatus of claim 1 wherein said logic means further includes comparison means for determining the larger and smaller of the horizontal and vertical deflection increments and means responsive to said comparison means for enabling said binary to unitary converter means to convert the larger, or both if equal, of said horizontal and vertical deflection increment signals into said binary word.
Claim 4
Dependent Claim
51 words
The apparatus of claim 2 wherein said logic means further includes distributing means responsive to said comparison means for converting the smaller of unequal horizontal and vertical deflection increment signals into another binary word having the 1''s distributed in accordance with the relative values of the larger and smaller increment signals.
Claim 5
Dependent Claim
65 words
The apparatus of claim 3 wherein said distributing means includes a matrix circuit having input rows corresponding to the possible combinations of larger and smaller increments and output columns corresponding to positions in said another binary word, each of said rows being connected to the columns corresponding to the distribution of 1''s in said another binary word for that combination of larger and smaller increments.
Claim 6
Dependent Claim
28 words
The apparatus of claim 4 wherein said logic means further includes means for converting said binary word and said another binary word into said respective binary bit streams.
Claim 7
Dependent Claim
86 words
The apparatus of claim 2 wherein said logic means further includes count down means, means for setting said count down means to the larger value of said increments, means for decrementing said count down means in synchronism with the application of stroke signals to said deflection circuits, means responsive to the decrementing of said count down means to a predetermined number for generating an end-of-stroke signal, and means responsive to said end-of-stroke signal for controlling said memory means to provide the next sequential line segment word.