Patent US3810029A successfully refreshed from Google Patents.
US3810029A
Expired / Lapsed
US
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System for detecting weak information signals in noisy receiver signals
Assignee: Gouvernement de la Republique Francaise
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Filing: 1973-05-18
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Granted: 1974-05-07
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Expires: 1993-05-18
Abstract
Abstract A system is provided which permits the detection of a useful signal in a received signal having a low signal to noise ratio. The system includes a band pass filter connected to receive the signal to be processed, an AGC amplifier, and a comparator which compares the output of the amplifier with a threshold or reference level and produces an output during the time this level is exceeded. The output of the comparator is converted into a train of rectangular pulses which are sampled at a clock frequency which is substantially shorter than the minimum duration of the useful signal. A circulating memory receives the samples which are arithmetically summed at each clock time, the arithmetical sum being then compared with a second threshold level to determine whether the received signal is a useful signal.
Inventors
- 👤 R Barthelemy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 07:22
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/02; G01S7/28; G01S7/285; G01S7/292; G01S7/2921; H; H03; H03D; H03D1/00; H03D1/02; H03D1/04
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
162 words
A system for detecting a weak useful signal in a noisy received signal, said system comprising a relatively narrow band, band pass filter connected to receive the signal to be processed, an automatic gain control amplifier connected to the output of said filter and providing a gain which is automatically variable in accordance with the output of said filter, a comparator circuit connected to the output of said amplifier for producing an output when said amplifier output exceeds a threshold level, means for converting the output of said comparator circuit into a pulse train of corresponding continuous rectangular pulses, means for sampling said rectangular pulses at a fixed clock frequency which is substantially shorter than the minimum duration of a useful signal, circulating memory means for receiving the samples, summing means for arithmetically summing the pulses stored in said circulating memory at each clock time, and a decision circuit for comparing the arithmetical sum of said pulses with a second threshold level.
Claim 2
Independent Claim
162 words
A system for detecting a weak useful signal in a noisy received signal, said system comprising a relatively narrow band, band pass filter connected to receive the signal to be processed, an automatic gain control amplifier connected to the output of said filter and providing a gain which is automatically variable in accordance with the output of said filter, a comparator circuit connected to the output of said amplifier for producing an output when said amplifier output exceeds a threshold level, means for converting the output of said comparator circuit into a pulse train of corresponding continuous rectangular pulses, means for sampling said rectangular pulses at a fixed clock frequency which is substantially shorter than the minimum duration of a useful signal, circulating memory means for receiving the samples, summing means for arithmetically summing the pulses stored in said circulating memory at each clock time, and a decision circuit for comparing the arithmetical sum of said pulses with a second threshold level.
Claim 3
Dependent Claim
53 words
A system as claimed in claim 1 wherein said first threshold level is produced by a further comparator circuit including first input connected to receive a voltage which is a function of the average power of the receiVed signal to be processed and a second input connected to an adjustable D.C. voltage source.
Claim 4
Dependent Claim
88 words
A system as claimed in claim 1 wherein said sampling means comprises first and second series-connected monostable multivibrators and an OR gate connected to the output of each of said multivibrators, the triggering time of said first multivibrator being between about 0.6 to 0.8T and the triggering time of the second multivibrator being between about 0.7 to 0.5T, where T is the inverse of the average frequency of the received signal, the total duration of the two multivibrators being greater than the longest period of the received signal.
Claim 5
Dependent Claim
46 words
A system as claimed in claim 3 wherein said sampling means is controlled by a clock frequency generator means which produces a clock frequency equal to the frequency of received signal, said clock frequency generator means comprising at least one amplifier and a pulse shaping circuit.
Claim 6
Dependent Claim
130 words
A system as claimed in claim 3 wherein said sampling means is controlled by a clock frequency generating circuit comprising a further OR gate having a first input connected to the output of said first multivibrator and a second input connected to the output of an AND gate, said system further comprising an oscillator producing an output kf, where k is a whole number, and a frequency divider for dividing the output of said oscillator by k, the said AND gate including a first input connected to the output of said frequency divider and second input connected to the inverted output of the first mentioned OR gate, said inverted output controlling actuation of said divider and a monostable shaping circuit being connected to the output of said further OR gate.
Claim 7
Dependent Claim
33 words
A system as claimed in claim 1 wherein said circulating memory means is controlled by a clock frequency generator which produces a clock advance frequency which is a sub-multiple of said clock frequency.
Claim 8
Dependent Claim
21 words
A system as claimed in claim 6 further comprising a majority filtering circuit connected in front of said circulating memory means.
Claim 9
Dependent Claim
21 words
A system as claimed in claim 1 wherein said summing means comprises digital summing means including a digital to analog converter.
Claim 10
Dependent Claim
15 words
A system as claimed in claim 1 wherein said summing means comprises analog summing means.
Claim 11
Dependent Claim
16 words
A system as claimed in claim 1 wherein said circulating memory means comprises a shift register.
Claim 12
Dependent Claim
36 words
A system as claimed in claim 10 wherein said summing means comprises a resistor ladder network with one resistor individually connected to each stage of said shift register and all resistors connected to a common point.
Claim 13
Dependent Claim
37 words
A system as claimed in claim 1 wherein said system comprises a first shift register, a first summing circuit, a threshold circuit, a second shift register, a second summing circuit and a decision circuit connected in series.
Claim 14
Dependent Claim
58 words
A system as claimed in claim 12 further comprising a frequency divider circuit connected between a clock frequency generator for generating said clock frequency and the clock advance input of said first shift register and a second, independently variable frequency divider circuit connected between said clock frequency generator and the clock advance input of said second shift register.
Claim 15
Dependent Claim
15 words
A receiver for an active sounding device including a system as claimed in claim 11.
Claim 16
Dependent Claim
17 words
A receiver for an active sounding device including a signal processing system as claimed in claim 13.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-05-06 | 1977-11-05 | 1978-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-05-06 | 1981-11-05 | 1982-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-05-06 | 1985-11-05 | 1986-05-07 | $7700.00 | Window Closed / Lapsed |