Logic system

Claim 2

A logic system comprising: shift register means having inputs and outputs, state counter means having inputs and outputs, a source of clock pulses, an array of logic gate means responsive to said clock pulses and digital counts from said shift register means and state counter means outputs to apply digital counts to said shift register means inputs and to said state counter means inputs.

Claim 3

A logic system as recited in claim 1 wherein there is provided an external source of digital pulses, and means for applying pulses from said external source of digital pulses to said array of logic gate means to enable said logic gate means to alter the count in said shift register means.

Claim 4

A logic system as recited in claim 1 wherein said logic gate means includes gate means for generating a display code output responsive to predetermined digital count inputs to said logic gate means from said shift register means and said state counter means, and display means responsive to said display code for visually displaying digits represented by said display code.

Claim 5

A logic system as recited in claim 3 wherein said gate means for generating a display code output responsive to digitaL count inputs to said logic gate means from said shift register means and said state counter means includes, means responsive to the outputs of said shift register means for generating display outputs, means responsive to the outputs of said state counter means for generating different display strobe signals, and means for applying said display outputs and said display strobe signals to actuate said display means.

Claim 6

A logic system as recited in claim 1 wherein said shift register means includes first shift register means and second shift register means, said logic gate means includes means for applying said predetermined digital counts to said first shift register means for circulation back into said logic gate means, and said logic gate means further includes means responsive to digital counts received from said second shift register means and state counter means outputs for entering other digital counts into said second shift register means and said state counter means.

Claim 7

A logic system as recited in claim 5 wherein there is included a transfer flip-flop and a compare flip-flop: means in said logic gate means responsive to a first predetermined count of said state counter for driving said compare flip-flop to its set state, means in said logic gate means responsive to a predetermined count state in the output of said second shift register and said compare flip-flop being in its set state for driving said transfer flip-flop to its set state, means in said logic gate responsive to said transfer flip-flop being in its set state to transfer the contents of said second shift register into said first shift register, and means in said logic means responsive to a second predetermined count of said state counter for resetting said transfer flip-flop and thus terminating from the transfer of the contents of said second register into said first register.

Claim 8

A logic system as recited in claim 1 wherein said array of logic gate means includes an array of AND gate means having inputs connected to said shift register means and state counter means outputs for generating decoding signals responsive thereto, an array of OR gate means having inputs connected to receive said decoding signals for generating different digital counts responsive thereto, and means for applying said different digital count outputs of said array of OR gate means to the inputs to said shift register means and said state counter means.

Claim 9

A logic system comprising shift register means having inputs and outputs: state counter means having inputs and outputs, a source of clock pulses, means for applying clock pulses to said shift register means to cause it to shift, an array of AND gate means connected to receive count outputs from said state counter means and said shift register means and clock pulses for producing first outputs and strobe outputs, an array of OR gate means connected to receive first outputs from said AND gate means for producing responsive thereto different count outputs for said state counter and shift register and display outputs, means for applying said different count outputs respectively to said state counter means and to said shift register means, display means, and means for applying said display outputs and strobe outputs to said display means to be displayed.

Claim 10

A logic system comprising shift register means having inputs and outputs: state counter means having inputs and outputs, a source of clock pulses, means for applying clock pulses to said shift register means to cause it to shift, an array of AND gate means connected to receive count outputs from said state counter means and said shift register means and clock pulses for producing first outputs and strobe outputs, an array of OR gate means connected to receive first outputs from said AND gate means for producing responsive thereto different count outputs for said state counter and shift register and display outputs, means for applying said different count outputs respectively to said state counter means and to said shift register means, display means, and means for applying said display outputs and strobe outputs to said display means to be displayed.

Claim 11

A logic system comprising a first and a second shift register means respectively, having first and second inputs and first and second outputs: state counter means having inputs and outputs, a source of clock pulses, an external digital pulse source, an array of AND gate means responsive to said state counter means outputs, said first and second shift register outputs, clock pulses and pulses from said digital pulse source to provide first outputs and display strobe pulses, an array of OR gate means responsive to said first outputs for providing state counter count outpUts, shift register count outputs and display outputs, means for applying said respective state counter and shift register outputs to said state counter and first and second shift register inputs, display means, and means for applying said display strobe pulses and display outputs to said display means to enable it to display information representative of said display outputs.

Claim 12

A logic system comprising a first and a second shift register means respectively, having first and second inputs and first and second outputs: state counter means having inputs and outputs, a source of clock pulses, an external digital pulse source, an array of AND gate means responsive to said state counter means outputs, said first and second shift register outputs, clock pulses and pulses from said digital pulse source to provide first outputs and display strobe pulses, an array of OR gate means responsive to said first outputs for providing state counter count outpUts, shift register count outputs and display outputs, means for applying said respective state counter and shift register outputs to said state counter and first and second shift register inputs, display means, and means for applying said display strobe pulses and display outputs to said display means to enable it to display information representative of said display outputs.

Claim 13

A logic system as recited in claim 9 wherein said AND gate means and said OR gate means responsive to a predetermined count from said state counter means recirculates the output of said second shift register means to the input to said second shift register means.

Claim 14

A logic system as recited in claim 9 wherein said AND gate means and OR gate means include logic gate means responsive to receiving a predetermined count from said state counter means and from said first shift register means to transfer the contents of said first shift register means into said second shift register means through said OR gate and said AND gate means.

Claim 15

A logic system comprising: an array of AND gate means having inputs connected for providing first outputs responsive to predetermined digital logic signal patterns, an array of OR gate means having inputs connected for providing digital logic signal outputs responsive to said first outputs, state counter means having inputs connected to receive some of the digital logic signal outputs from said array of OR gate means and having outputs connected to some of the inputs of said AND gate means, and shift register means having inputs connected to receive others of the digital logic signal outputs from said array of OR gate means and having outputs connected to others of the inputs of said AND gate means.

Claim 16

A logic system comprising: an array of AND gate means having inputs connected for providing first outputs responsive to predetermined digital logic signal patterns, an array of OR gate means having inputs connected for providing digital logic signal outputs responsive to said first outputs, state counter means having inputs connected to receive some of the digital logic signal outputs from said array of OR gate means and having outputs connected to some of the inputs of said AND gate means, and shift register means having inputs connected to receive others of the digital logic signal outputs from said array of OR gate means and having outputs connected to others of the inputs of said AND gate means.

Claim 17

A logic system as recited in claim 12 wherein said logic system includes display means responsive to some of said digital logic outputs from said array of OR gate means for visually indicating digital data representative of said digital logic.

Claim 18

A logic system as recited in claim 13 wherein said array of AND gate means includes means responsive to the outputs of said shift register means for generating display encoded outputs, said array of OR gate means include means responsive to the display encoded outputs for generating decoded display outputs, said array of AND gate means includes means responsive to predetermined counts of said state counter for producing different display strobe signals, and means for applying said decoded display outputs and said different display strobe signals to actuate said display means.

Claim 19

A logic system as recited in claim 12 wherein there is included a source of clock pulses: means for applying clock pulses to said shift register means and to said array of AND gate means to actuate said shift register and said array of AND gate means, said AND gate means and OR gate means including means responsive to the digital logic output signals of said state counter means and said shift register means for inserting into said state counter means and shift register means incremented digital data.

Claim 20

A logic system as recited in claim 13 wherein said OR gate means inserts into said shift register means said AND gate means first outputs responsive to which said OR gate means provide some digital logic outputs to which said display means is responsive.

Claim 21

A logic system as recited in claim 16 wherein said shift register means into which said OR gate means inserts said AND gate means first outputs includes a display shift register means for circulating between said OR gate means and said AND gate means data representative of data to be displayed from the outputs of said array of OR gate means, and data shift register means for circulating digital data from the outputs of said array of OR gate means to the inputs to said array of AND gate means.