Error detection and correction apparatus for use in a magnetic tape system

Claim 2

Apparatus for detecting potential failure within any one of a plurality of information channels of a storage system, said plurality of information channels including a corresponding number of sense circuits, the sense circuit of each channel being operative to provide pulses representative of information to first and second output lines, said pulses applied to said first line representing a binary ONE and said pulses applied to said second line representing a binary ZERO, each sense circuit providing at least one pulse during each bit interval and each byte of information corresponding to a group of bit signals simultaneously recorded on the medium being read and applied to said information channels, said apparatus comprising: a plurality of deskewing buffer registers, each of said registers including first and second bistable storage means; said first and second bistable storage means of a first one of said buffer registers of each information channel being coupled to receive said pulses applied to said first and second lines respectively of a corresponding one of said sense circuits and including means for receiving first and second sets of clocking signals defining a bit interval; sensing means individually coupled to said first and second bistable means of said first register of said each information channel, said sensing means being operative in response to a predetermined one of said clocking signals to produce a first output signal when said first and second bistable means are in different states signaling the occurrence of an overskew condition within said information channel; and, bistable channel failure indicator means coupled to said sensing means of said each channel, said channel failure indicator means being conditioned by said output signal to switch from a first to a second state indicative of said potential failure within said channel associated therewith.

Claim 3

The apparatus of claim 1 further including first and second synchronous bistable storage elements coupled to receive first and second sets of asynchronous clocking signals respectively, each of said first and second bistable means including means for receiving synchronous clocking signals, said first and second bistable elements being conditioned by said synchronous clocking signals to switch from a first to a second state in response to said sets of asynchronous clocking signals to produce said clocking signals.

Claim 4

The apparatus of claim 1 further including: means coupled to said channel failure indicator means of said each channel and to said first and second bistable storage means of a predetermined one of said deskewing buffer registers, said means being conditioned by said indicator means when in said second state to force said first and second bistable means to a predetermined state during succeeding bit intervals signaling that the information within said failed channel requires correction.

Claim 5

The apparatus of claim 3 further including means coupled to said channel failure indicator means, said means being conditioned by said channel failure indicator means to produce a signal to inhibit the generation of said clockiNg signals when said channel failure indicator means switches to said second state.

Claim 6

The apparatus of claim 3 further including: checking means coupled to a last one of said buffer registers, said checking means being operative to perform a vertical check upon the information contents of each of said bistable means of each channel corresponding to an assembled byte of information, said checking means being operative in accordance with the results of said vertical check to generate an error correction signal signaling that the information stored in said first bistable means of said failed channel requires modification; and, logic gating means coupled to said first bistable means of said last one of said buffer registers of each information channel, said logic gating means of said channel signaling said failure being conditioned by said signal to transfer selectively the contents of said first bistable means to correct a corresponding one of the bit positions of said assembled byte.

Claim 7

The apparatus of claim 4 wherein said checking means includes: parity generation means, said parity generation means being operative to generate an odd parity check signal for said assembled byte; and, gating means coupled to said parity generation means, said gating means being conditioned by said check signal to force said output signal to a binary ONE and a binary ZERO respectively when the information in said failed channel is representative of a binary ONE and a binary ZERO.

Claim 8

The apparatus of claim 5 further including: logic gating means coupled to said first and second bistable means of said last one of said registers of each of said information channels, said gating means being operative to generate a signal when said first and second bistable means are both in a binary ONE state indicating that the information within said failed channel is to be corrected; and, multi-stage data register means coupled to receive said assembled byte signals from said last one of said buffer registers, each stage of said data register means including a pair of input gating means, one of said of pair being coupled individually to one of said first bistable means of said last one of said registers of said information channel and to said checking means, the other one of said pair being coupled to said first bistable means and to said sensing means of said information channel, said other one of said gating means being conditioned by said signal from said gating means to inhibit the transfer of the information contents of said first bistable means and said other one of said gating means being conditioned by said signal from said checking means to transfer selectively said information contents of said first bistable means.

Claim 9

The apparatus of claim 5 wherein each of said pairs of input gating means include an AND gate.

Claim 10

The apparatus of claim 1 further including: logic sensing means individually coupled to said first and second means of said first register of said each channel, said sensing means being conditioned by said first and second bistable means when both are in the same predetermined state to generate a second output signal signaling the occurrence of a dropped pulse within said channel; and, counting means coupled to said logic sensing means and to each said channel failure indicator means, said counting means including logic means, said logic means being operative in response to said second output signal from counting a predetermined number of consecutive dropped pulses within said channel to switch said channel failure indicator means to said second state.

Claim 11

The apparatus of claim 9 further including means coupled to said channel failure indicator means, said means being conditioned by said channel failure indicator means to produce a signal to inhibit generation of said clocking signals when said channel failure indicator means switches to said second state.

Claim 12

The apparatus of claim 9 further including: clockIng means coupled to said means for separately applying said first and second sets of synchronous clocking signals to said each channel, said predetermined number of dropped pulses being selected in accordance with the operating characteristics of said clocking means.

Claim 13

The apparatus of claim 11 wherein said predetermined number corresponds to three.

Claim 14

A data recovery system for reliably processing information signals recorded within a plurality of channels as a series of transitions occurring within a corresponding number of bit intervals, at least one transition occurring within each bit interval, said system comprising: a plurality of deskewing buffer register means for accommodating a skew of a predetermined maximum number of bit positions, each of said register means including a pair of bistable storage means, each pair of a first one of said register means being individually associated with one of said channels for receiving pulses representative of binary ONE and binary ZERO data defined by said transitions; means for applying first and second sets of clocking signals defining the beginning and end of said bit intervals to first and second bistable storage means respectively of each pair of said first one of said register means for switching said pair from a first state to second and third states in response to pulses received during said bit intervals; logic sensing means individually coupled to each pair of bistable storage means of a last one of said register means, said sensing means being conditioned by said each pair when in a fourth state to generate a first output signal signaling an occurrence of a dropped bit within said channel; counting means coupled to said logic sensing means, said counting means being operative to count consecutive occurrences of said first output signal, said counting means including means being operative to produce a second output signal when said counting means advances to a predetermined count; and, bistable channel failure indicator storage means coupled to said means of said counting means and to a pair of a predetermined one of said buffer register means, said channel indicator means being operative in response to said second output signal to switch to a predetermined state signaling a potential failure within said channel, said pair being operative in response to said second output signal to switch to said fourth state during each successive bit interval.

Claim 15

A data recovery system for reliably processing information signals recorded within a plurality of channels as a series of transitions occurring within a corresponding number of bit intervals, at least one transition occurring within each bit interval, said system comprising: a plurality of deskewing buffer register means for accommodating a skew of a predetermined maximum number of bit positions, each of said register means including a pair of bistable storage means, each pair of a first one of said register means being individually associated with one of said channels for receiving pulses representative of binary ONE and binary ZERO data defined by said transitions; means for applying first and second sets of clocking signals defining the beginning and end of said bit intervals to first and second bistable storage means respectively of each pair of said first one of said register means for switching said pair from a first state to second and third states in response to pulses received during said bit intervals; logic sensing means individually coupled to each pair of bistable storage means of a last one of said register means, said sensing means being conditioned by said each pair when in a fourth state to generate a first output signal signaling an occurrence of a dropped bit within said channel; counting means coupled to said logic sensing means, said counting means being operative to count consecutive occurrences of said first output signal, said counting means including means being operative to produce a second output signal when said counting means advances to a predetermined count; and, bistable channel failure indicator storage means coupled to said means of said counting means and to a pair of a predetermined one of said buffer register means, said channel indicator means being operative in response to said second output signal to switch to a predetermined state signaling a potential failure within said channel, said pair being operative in response to said second output signal to switch to said fourth state during each successive bit interval.

Claim 16

The system of claim 13 further including: means coupled to said channel failure indicator means of said each channel and to said first and second bistable storage means of a predetermined one of said deskewing buffer register means, said means being conditioned by said indicator means when in said predetermined state to force said first and second bistable means to a predetermined state during succeeding bit intervals signaling that the information within said failed channel requires correction.

Claim 17

The system of claim 14 further including means coupled to said channel failure indicator means, said means being conditioned by said channel failure indicator means to produce a signal to inhibit generation of said clocking signals when said channel failure indicator means switches to said second state.

Claim 18

The system of claim 14 further including: checking means coupled to a last one of said buffer registers, said checking means being operative to perform a vertical check upon the information contents of each of said bistable means of each channel corresponding to as assembled byte of information, said checking means being operative in accordance with the results of said vertical check to generate an error correction signal signaling that the information stored in said first bistable means of said failed channel requires modification; and, logic gating means coupled to said first bistable means of said last one of said buffer registers of each information channel, said logic gating means of said channel signaling saId failure being conditioned by said signal to transfer selectively the contents of said first bistable means to correct a corresponding one of the bit positions of said assembled byte.

Claim 19

The system of claim 16 further including: logic gating means coupled to said first and second bistable means of said last one of said registers of each of said information channels, said gating means being operative to generate a signal when said first and second bistable means are both in a binary ONE state indicating that the information within said failed channel is to be corrected; and, multi-stage data register means coupled to receive said assembled byte signals from said last one of said buffer registers, each stage of said data register means including a pair of input gating means, one of said pair being coupled individually to one of said first bistable means of said last one of said registers of said information channel and to said checking means, the other one of said pair being coupled to said first bistable means and to said sensing means of said information channel, said other one of said gating means being conditioned by said signal from said gating means to inhibit the transfer of the information contents of said first bistable means and said other one of said gating means being conditioned by said signal from said checking means to transfer selectively said information contents of said first bistable means.

Claim 20

The system of claim 16 wherein said checking means includes: parity generation means, said parity generation means being operative to generate an odd parity check signal for said assembled byte; and, gating means coupled to said parity generation means, said gating means being conditioned by said check signal to force said output signal to a binary ONE and a binary ZERO respectively when the information in said failed channel is representative of a binary ONE and a binary ZERO.

Claim 21

The system of claim 14 further including: clocking means coupled to said means for separately applying said first and second sets of synchronous clocking signals to said each channel, said predetermined number of dropped pulses being selected in accordance with the operating characteristics of said clocking means.

Claim 22

The system of claim 19 wherein said predetermined number corresponds to three.

Claim 23

The system of claim 20 wherein said predetermined maximum number of bit positions corresponds to three.

Claim 24

In an information processing system, apparatus for detecting a potential failure occurring during a transfer of information through one of a plurality of information channels, each of said channels including a sense circuit operative to provide pulses representative of a bit of information to first and second output lines, each byte of information corresponding to a group of bit signals simultaneously recorded on a medium being read, and said each channel further including a predetermined maximum number of series coupled deskewing buffer registers, each of said registers including first and second bistable storage means, said first and second bistable storage means of a first one of said buffer registers of each information channel being coupled to receive said pulses applied to said first and second lines respectively and first and second sets of clocking signals defining a bit interval, said apparatus comprising: sensing means coupled to said first and second bistable storage means of a predetermined one of said plurality of deskewing buffer registers, said sensing means being operative when said first and second bistable means are in different states to produce a first output signal in response to one of said clocking signals signaling the occurrence of an overskew condition within said channel; and, bistable channel failure indicator means coupled to said sensing means, said channel failure indicator means being conditioned by said output signal to switch from a first to a second state signaling the detection of a pOtential failure within said channel.

Claim 25

In an information processing system, apparatus for detecting a potential failure occurring during a transfer of information through one of a plurality of information channels, each of said channels including a sense circuit operative to provide pulses representative of a bit of information to first and second output lines, each byte of information corresponding to a group of bit signals simultaneously recorded on a medium being read, and said each channel further including a predetermined maximum number of series coupled deskewing buffer registers, each of said registers including first and second bistable storage means, said first and second bistable storage means of a first one of said buffer registers of each information channel being coupled to receive said pulses applied to said first and second lines respectively and first and second sets of clocking signals defining a bit interval, said apparatus comprising: sensing means coupled to said first and second bistable storage means of a predetermined one of said plurality of deskewing buffer registers, said sensing means being operative when said first and second bistable means are in different states to produce a first output signal in response to one of said clocking signals signaling the occurrence of an overskew condition within said channel; and, bistable channel failure indicator means coupled to said sensing means, said channel failure indicator means being conditioned by said output signal to switch from a first to a second state signaling the detection of a pOtential failure within said channel.

Claim 26

The system of claim 22 wherein said apparatus further includes: means coupled to said channel failure indicator means and to said first and second bistable storage means of a predetermined one of said registers, said means being operative to force said first and second bistable storage means to a predetermined state when said channel failure indicator means is in said second state during succeeding bit intervals signaling that the information being transferred through said channel requires correction.

Claim 27

The system of claim 23 further including: checking means coupled to each of said first bistable storage means of a last one of said buffer registers of each channel, said checking means being operative to perform a vertical check upon the contents of each of said first bistable means corresponding to an assembled byte of information, said checking means being operative in accordance with the results of said vertical check to generate a signal indicating when information being transferred through a channel requires modification; and, logic gating means coupled to said first bistable means of said last one of said buffer registers of each information channel, said logic gating means of said channel signaling said failure being conditioned by said signal to transfer selectively the contents of said first bistable means to correct a corresponding one of the bit positions to said assembled byte.

Claim 28

The system of claim 24 further including: logic gating means coupled to said first and second bistable means of said last one of said registers of each of said information channels, said gating means being operative to generate a signal when said first and second bistable means are both in a binary ONE state indicating that the information within said failed channel is to be corrected; and, multi-stage data register means coupled to receive said assembled byte signals from said last one of said buffer registers, each stage of said data register means including a pair of input gating means, one of said pair being coupled individually to one of said first bistable means of said last one of said registers of said information channel and to said checking means, the other one of said pair being coupled to said first bistable means and to said sensing means of said information channel, said other one of said gating means being conditioned by said signal from said gating means to inhibit the transfer of the information contents of said first bistable means and said other one of said gating means being conditioned by said signal from said checking means to transfer selectively said information contents of said first bistable means.

Claim 29

The system of claim 24 wherein said checking means includes: parity generation means, said parity generation means being operative to generate an odd parity check signal for said assembled byte; and, gating means coupled to said parity generation means, said gating means being conditioned by said check signal to force said output signal to a binary ONE and a binary ZERO respectively when the information in said failed channel is representative of a binary ONE and a binary ZERO.

Claim 30

In an information processing system, apparatus for detecting a potential failure occurring during a transfer of information through one of a plurality of information channels, each of said channels including a sense circuit operative to provide pulses representative of a bit of information to first and second output lines, each byte of information corresponding to a group of bit signals simultaneously recorded on a medium being read, and said each channel further including a predetermined maximum number of series coupled deskewing buffer registers, each of said registers including first and second bistable storage means, said first and second bistable storage means of a first one of said buffer registers of each information channel being coupled to receive said pulses applied tO said first and second lines respectively and first and second sets of clocking signals defining a bit interval, said apparatus comprising: logic sensing means individually coupled to said first and second means of said first register of said each channel, said sensing means being conditioned by said first and second bistable means when both are in the same predetermined state to generate a second output signal signaling the occurrence of a dropped pulse within said channel; and, counting means coupled to said logic sensing means and to each said channel failure indicator means, said counting means including logic means, said logic means being operative in response to said second output signal from counting a predetermined number of consecutive dropped pulses within said channel to switch said channel failure indicator means to said second state.

Claim 31

In an information processing system, apparatus for detecting a potential failure occurring during a transfer of information through one of a plurality of information channels, each of said channels including a sense circuit operative to provide pulses representative of a bit of information to first and second output lines, each byte of information corresponding to a group of bit signals simultaneously recorded on a medium being read, and said each channel further including a predetermined maximum number of series coupled deskewing buffer registers, each of said registers including first and second bistable storage means, said first and second bistable storage means of a first one of said buffer registers of each information channel being coupled to receive said pulses applied tO said first and second lines respectively and first and second sets of clocking signals defining a bit interval, said apparatus comprising: logic sensing means individually coupled to said first and second means of said first register of said each channel, said sensing means being conditioned by said first and second bistable means when both are in the same predetermined state to generate a second output signal signaling the occurrence of a dropped pulse within said channel; and, counting means coupled to said logic sensing means and to each said channel failure indicator means, said counting means including logic means, said logic means being operative in response to said second output signal from counting a predetermined number of consecutive dropped pulses within said channel to switch said channel failure indicator means to said second state.

Claim 32

The system of claim 27 wherein said predetermined number corresponds to three.

Claim 33

The system of claim 27 wherein said apparatus further includes: means coupled to said channel failure indicator means of said each channel and to said first and second bistable storage means of a predetermined one of said deskewing buffer register means, said means being conditioned by said indicator means when in said predetermined state to force said first and second bistable means to a predetermined state during succeeding bit intervals signaling that the information within said failed channel requires correction.

Claim 34

The system of claim 27 wherein said apparatus further includes: means coupled to said channel failure indicator means, said means being conditioned by said channel failure indicator means to produce a signal to inhibit generation of said clocking signals when said channel failure indicator means switches to said second state.