Surface charge signal correlator

Claim 2

A semiconductor device comprising: a substrate of semiconductor material of a first conductivity type; a first thin insulating layer overlying said substrate; first, second, and third adjacently spaced conductor means overlying said first thin insulating layer for forming first, second, and third carrier depletion regions having first and second barrier regions therebetween in said substrate; a second thin insulating layer overlying said first thin insulating layer and said first second and third conductor means; first and second control means each respectively overlying said second thin insulating layer and the spacing between said first and second conductor means for controlling said first barrier region; third and fourth control means each respectively overlying said second thin insulating layer and the spacing between said second and third conductor means for controlling said second barrier region; a region within said substrate of a second conductivity type, said region of a second conductivity type providing for both injection and removal of charge carriers into and from said first carrier depletion region; a third barrier region in said substrate between said region of a second conductivity type and said first carrier depletion region; and fifth control means overlying said second thin insulating layer and insulatingly overlying said third barrier region for controlling said third barrier region.

Claim 3

The device of claim 1 further including a non-rectifying contact in said region of a second conductivity type for applying an electrical signal to said region of a second conductivity type.

Claim 4

A semiconductor circuit module for determining the correlation between an analog signal and a digital reference word comprising: a substrate of semiconductor material of a first conductivity type having a region of a second conductivity type therein; a first insulating layer overlying said substrate, said first insulating layer having a plurality of thin insulating areas surrounded by thick insulating areas, said thin insulating areas defining a like plurality of information channels in said substrate; first, second, and third conductor means over-lying each said thin insulating area for forming first, second, and third carrier depletion regions having first and second barrier regions therebetween in said substrate, said first carrier depletion region and said region of a second conductivity type defining a third barrier region therebetween; a second insulating layer overlying said first insulating layer and said conductor means; first control means overlying each said thin insulating area and said second insulating layer and insulatingly overlying said first barrier region for controlling said first barrier region; second control means overlying each said thin insulating area and said second insulating layer and insulatingly overlying said second barrier region for controlling said second barrier region; third control means overlying each said thin insulating areA and said second insulating layer and insulatingly overlying said third barrier region for controlling said third barrier region; means for applying said analog signal to said region of a second conductivity type; means for sequentially applying a voltage to said third control means; means for serially receiving the bits of said digital reference word and providing voltage levels responsive to the value of said bits; means for applying said voltage levels to said first and second control means; and means for receiving electrical potential proportional to a quantity of charge contained in said first carrier depletion region, said electrical potential being proportional to the correlation between said analog signal and said digital reference word.

Claim 5

A semiconductor circuit module for determining the correlation between an analog signal and a digital reference word comprising: a substrate of semiconductor material of a first conductivity type having a region of a second conductivity type therein; a first insulating layer overlying said substrate, said first insulating layer having a plurality of thin insulating areas surrounded by thick insulating areas, said thin insulating areas defining a like plurality of information channels in said substrate; first, second, and third conductor means over-lying each said thin insulating area for forming first, second, and third carrier depletion regions having first and second barrier regions therebetween in said substrate, said first carrier depletion region and said region of a second conductivity type defining a third barrier region therebetween; a second insulating layer overlying said first insulating layer and said conductor means; first control means overlying each said thin insulating area and said second insulating layer and insulatingly overlying said first barrier region for controlling said first barrier region; second control means overlying each said thin insulating area and said second insulating layer and insulatingly overlying said second barrier region for controlling said second barrier region; third control means overlying each said thin insulating areA and said second insulating layer and insulatingly overlying said third barrier region for controlling said third barrier region; means for applying said analog signal to said region of a second conductivity type; means for sequentially applying a voltage to said third control means; means for serially receiving the bits of said digital reference word and providing voltage levels responsive to the value of said bits; means for applying said voltage levels to said first and second control means; and means for receiving electrical potential proportional to a quantity of charge contained in said first carrier depletion region, said electrical potential being proportional to the correlation between said analog signal and said digital reference word.

Claim 6

The circuit of claim 3 further including: means for receiving electrical potential proportional to a quantity of charge contained in said third carrier depletion region; and means connected between said means for receiving said electrical potentials for computing the difference in magnitude between said electrical potentials.

Claim 7

The circuit of claim 4 wherein said means for computing the difference in magnitude between said electrical potentials includes a differential amplifier.

Claim 8

The circuit of claim 3 wherein said means for applying said analog signal to said region of a second conductivity type includes a non-rectifying contact in said region of a second conductivity type.

Claim 9

The circuit of claim 3 wherein said means for sequentially applying a voltage to said third control means comprises: means for periodically generating voltage pulses; and shift register means for receiving said voltage pulses and for sequentially applying said voltage pulses to said third control means.

Claim 10

The circuit of claim 3 wherein said means for serially receiving the bits of said digital reference word and providing voltage levels responsive to the value of said bits includes a plurality of serially interconnected shift registers.

Claim 11

The circuit of claim 8 wherein each shift register of said plurality of serially interconnected shift registers has an inverting output and a non-inverting output, each said inverting output being connected to one said second control means and each said non-inverting output being connected to one said first control means.

Claim 12

The circuit of claim 3 wherein said means for receiving electrical potential includes a sample and hold circuit comprising: a capacitor having two conducting plates separated by a layer of insulting material, one of said conducting plates being connected to electrical ground; and switch means connected to the other of said conducting plates for periodically connecting said other conducting plate to said first conductor means.

Claim 13

The circuit of claim 3 further including: clock means for periodically raising and lowering said first and second barrier regions.

Claim 14

A signal correlator circuit comprising: a semiconductor substrate having a plurality of information channels therein, each said information channel having means defining first, second, and third charge storage regions therein; means responsive to a first periodic waveform for introducing each of a plurality of quantities of electrical charge, each said quantity of electrical charge being proportional to a corresponding one of a plurality of time division samples of an analog signal, into said first charge storage region of a corresponding one of said plurality of information channels; means responsive to a second periodic waveform for transferring said quantities of charge from said first charge storage regions to said second charge storage regions; means including a shift register responsive to a digital word for transferring said quantities of charge from said second charge storage regions to said first charge storage regions when a bit of said digital reference word has a first value and for transferring said quantities of charge from said second charge storage regions to said third charge storage regions when a bit of said digital reference word has a second value; and means for measuring the quantity of charge in said first charge storage regions.

Claim 15

A signal correlator circuit comprising: a semiconductor substrate having a plurality of information channels therein, each said information channel having means defining first, second, and third charge storage regions therein; means responsive to a first periodic waveform for introducing each of a plurality of quantities of electrical charge, each said quantity of electrical charge being proportional to a corresponding one of a plurality of time division samples of an analog signal, into said first charge storage region of a corresponding one of said plurality of information channels; means responsive to a second periodic waveform for transferring said quantities of charge from said first charge storage regions to said second charge storage regions; means including a shift register responsive to a digital word for transferring said quantities of charge from said second charge storage regions to said first charge storage regions when a bit of said digital reference word has a first value and for transferring said quantities of charge from said second charge storage regions to said third charge storage regions when a bit of said digital reference word has a second value; and means for measuring the quantity of charge in said first charge storage regions.

Claim 16

The correlator circuit of claim 12 further including: means for measuring the quantity of charge in said third charge storage regions; and means for computing the difference between the quantity of charge in said first charge storage regions and the quantity of charge in said third charge storage regions.

Claim 17

A signal correlator circuit comprising: a semiconductor substrate having a plurality of information channels therein, each said information channel having means defining first, second, and third charge storage regions therein; means for introducing a quantity of electrical charge proportional to one time division sample of an analog signal into said first charge storage region of one said information channel and for introducing a second quantity of electrical charge proportional to another time division sample of said analog signal into said first charge storage region of another said information channel, whereby a plurality of samples of said analog signal are assigned to and stored in said plurality of information channels on a one-for-one basis; means for transferring said quantities of charge from said first charge storage regions to said second charge storage regions; means for transferring said quantities of charge from said second charge storage regions to said first charge storage regions when a bit of a digital reference word has a first value; means for transferring said quantities of charge from said second charge storage regions to said third charge storage regions when a bit of a digital reference word has a second value; and means for measuring the quantity of charge in said first charge storage regions.

Claim 18

A signal correlator circuit comprising: a semiconductor substrate having a plurality of information channels therein, each said information channel having means defining first, second, and third charge storage regions therein; means for introducing a quantity of electrical charge proportional to one time division sample of an analog signal into said first charge storage region of one said information channel and for introducing a second quantity of electrical charge proportional to another time division sample of said analog signal into said first charge storage region of another said information channel, whereby a plurality of samples of said analog signal are assigned to and stored in said plurality of information channels on a one-for-one basis; means for transferring said quantities of charge from said first charge storage regions to said second charge storage regions; means for transferring said quantities of charge from said second charge storage regions to said first charge storage regions when a bit of a digital reference word has a first value; means for transferring said quantities of charge from said second charge storage regions to said third charge storage regions when a bit of a digital reference word has a second value; and means for measuring the quantity of charge in said first charge storage regions.