Patent US3798467A successfully refreshed from Google Patents.
US3798467A
Expired / Lapsed
US
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Circuit for interference free recognition of zero crossings of read signals of magnetic layer memories
Assignee: Siemens AG
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Filing: 1972-08-31
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Granted: 1974-03-19
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Expires: 1992-08-31
Abstract
Abstract A circuit for interference free recognition of zero crossings of differentiated read signals comprises a zero detector and a signal checking circuit for simultaneously receiving the read signals. The signal checking circuit comprises an amplitude evaluation circuit and a time evaluation circuit. The zero detector and the signal checking circuit are connected to an output circuit which provides an output pulse in response to an output signal from the zero detector and the signal checking circuit. The time evaluation circuit comprises a charging circuit including a capacitor which is charged in accordance with a first time constant when a differentiated read signal exceeds an amplitude evaluation level of the amplitude evaluation circuit and is discharged in accordance with a second time constant when the differentiated read signal is lower than the amplitude evaluation threshold.
Inventors
- 👤 W Gottwald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:38
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1536
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
336 words
A circuit for interference free recognition of zero crossings of differentiated read signals of magnetic layer memories, comprising: a zero crossing detector for receiving read signals and operable to emit an output pulse in response thereto; a signal checking circuit for receiving read signals simultaneously with said zero crossing detector, said signal checking circuit including an amplitude evaluation circuit having an amplitude evaluation threshold and a time evaluation circuit having a time evaluation threshold and operable to emit an output signal; and an output circuit operable to emit an output pulse in response to receipt of an output signal from said zero crossing detector and an output signal from said signal checking circuit, said time evaluation circuit comprising a charging circuit including a capacitor, means for charging said capacitor in accordance with a first time constant when a differentiated read signal exceeds the amplitude evaluation threshold of said amplitude evaluation circuit, means for discharging said capacitor in accordance with a second time constant when the differentiated read signal is lower than the amplitude evaluation threshold, and a threshold evaluation circuit connected to said charging circuit and operable to emit an output signal when the voltage on said capacitor becomes greater than its given threshold value, said charging circuit comprising said capacitor which has a first terminal connected to a first supply potential and a second terminal connected to said threshold evaluation circuit, said means for charging said capacitor comprises a first resistor connected between said second terminal and a second supply potential, said means for discharging said capacitor comprises a transistor having a base, an emitter and a collector, said emitter connected to the first supply potential, a diode connected between said collector and a third supply potential to limit the potential at said second terminal of said capacitor, a second resistor connected between said collector and said second terminal of said capacitor, said transistor being blocked in response to the application of a differentiated read signal to said base which exceeds the amplitude evaluation threshold.
Claim 2
Dependent Claim
336 words
A circuit for interference free recognition of zero crossings of differentiated read signals of magnetic layer memories, comprising: a zero crossing detector for receiving read signals and operable to emit an output pulse in response thereto; a signal checking circuit for receiving read signals simultaneously with said zero crossing detector, said signal checking circuit including an amplitude evaluation circuit having an amplitude evaluation threshold and a time evaluation circuit having a time evaluation threshold and operable to emit an output signal; and an output circuit operable to emit an output pulse in response to receipt of an output signal from said zero crossing detector and an output signal from said signal checking circuit, said time evaluation circuit comprising a charging circuit including a capacitor, means for charging said capacitor in accordance with a first time constant when a differentiated read signal exceeds the amplitude evaluation threshold of said amplitude evaluation circuit, means for discharging said capacitor in accordance with a second time constant when the differentiated read signal is lower than the amplitude evaluation threshold, and a threshold evaluation circuit connected to said charging circuit and operable to emit an output signal when the voltage on said capacitor becomes greater than its given threshold value, said charging circuit comprising said capacitor which has a first terminal connected to a first supply potential and a second terminal connected to said threshold evaluation circuit, said means for charging said capacitor comprises a first resistor connected between said second terminal and a second supply potential, said means for discharging said capacitor comprises a transistor having a base, an emitter and a collector, said emitter connected to the first supply potential, a diode connected between said collector and a third supply potential to limit the potential at said second terminal of said capacitor, a second resistor connected between said collector and said second terminal of said capacitor, said transistor being blocked in response to the application of a differentiated read signal to said base which exceeds the amplitude evaluation threshold.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-18 | 1977-09-17 | 1978-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-18 | 1981-09-17 | 1982-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-18 | 1985-09-17 | 1986-03-19 | $7700.00 | Window Closed / Lapsed |