Electronic device for quintupling a binary-coded decimal number

Claim 1

An electronic device for quintupling a binary-coded decimal number, comprising: pulse generating means for generating a series of at least four clock pulses and a plurality of time displaced sequential pulses, said time displaced pulses representing the binary weights of a binary-coded decimal number to be multiplied, said plurality of time displaced pulses including first, second and third pulses corresponding respectively to the first clock pulse of said series of four pulses, the third clock pulse of said series and the complement of the fourth clock pulse of said series; adding means having first and second inputs for adding two binary-coded numbers; first, second and third serially connected delay circuits, said first delay circuit having an input signal representing a quantity to be multiplied by five applied thereto, said pulse generating means being coupled to said delay circuits to supply clock pulses thereto, the output of each delay circuit being delayed by one clock pulse; a first AND gate circuit having a first input to which said input signal representing the quantity to be multiplied is applied and a second input to which said first time displaced pulse from said pulse generating means is applied; a second AND gate circuit having a first input coupled with the output of said second delay circuit and a second input to which said second time displaced pulse is applied; an OR gate circuit having first and second inputs coupled to the outputs of said first and second AND gates, respectively, the output of said OR gate being coupled to said first input of said adding means; and a third AND gate circuit having a first input coupled to the output of said third delay circuit and a second input to which said third displaced pulse is applied, the output of said third AND gate circuit being coupled to said second input of said adding means.