Patent US3630608A successfully refreshed from Google Patents.
Patent US3796996A successfully refreshed from Google Patents.
US3796996A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Main memory reconfiguration
Assignee: Bull HN Information Systems Italia SpA
•
Filing: 1972-10-05
•
Granted: 1974-03-12
•
Expires: 1992-10-05
Abstract
Abstract An apparatus and a method for reconfiguring an m-module m-way interleaved main memory store to a k-way interleaved configuration where k equals m/2. In a main memory store having m modules and operating in an n-way interleaved configuration L additional reconfiguration modes allow the isolation of any one bad module in the upper half of the memory addressing range, thus giving assurance of operation in the lower half of the memory addressing range. The remaining lower half of the memory system remains addressable so that diagnostic procedures may be run in that portion of memory simultaneously with the running of user programs on the other portion of memory.
Inventors
- 👤 J Curley
- 👤 B Franklin
- 👤 W Martland
- 👤 T Donahue
- 👤 L Cornaro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:31
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G06; G06F; G06F12/00; G06F12/02; G06F12/04; G06F12/06; G06F12/0607; G06F12/08; G06F12/0802; G06F13/00; G06F13/14; G06F13/16; G06F13/18
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
182 words
In combination with a computer memory system comprised of four memory modules arranged in an four-way interleaved addressing configuration mode, an electrical reconfiguration network for dynamically varying under program control the configuration mode of said four memory modules from four way interleaved addressing configuration to two-way interleaved addressing configuration where k is an integer equal to m/2, said reconfiguration network comprising: a. first circuit means responsive to first predetermined bits in a first instruction from a program under execution for generating first reconfiguration signals, indicative of a desired predetermined state of interleaved addressing configuration; b. second circuit means responsive to second predetermined addressing bit positions in a second instruction of a program under execution for generating second reconfiguration signals; c. third means, responsive to said second means, for addressing predetermined ones of said four modules in normal four-way interleaved addressing configuration; and d. fourth circuit means, coupled to said first and second circuit means, for dynamically varying, in response to said first or second reconfiguration signals, the configuration mode of said four modules from four-way interleaved addressing configuration to two-way interleaved addressing.
Claim 2
Dependent Claim
182 words
In combination with a computer memory system comprised of four memory modules arranged in an four-way interleaved addressing configuration mode, an electrical reconfiguration network for dynamically varying under program control the configuration mode of said four memory modules from four way interleaved addressing configuration to two-way interleaved addressing configuration where k is an integer equal to m/2, said reconfiguration network comprising: a. first circuit means responsive to first predetermined bits in a first instruction from a program under execution for generating first reconfiguration signals, indicative of a desired predetermined state of interleaved addressing configuration; b. second circuit means responsive to second predetermined addressing bit positions in a second instruction of a program under execution for generating second reconfiguration signals; c. third means, responsive to said second means, for addressing predetermined ones of said four modules in normal four-way interleaved addressing configuration; and d. fourth circuit means, coupled to said first and second circuit means, for dynamically varying, in response to said first or second reconfiguration signals, the configuration mode of said four modules from four-way interleaved addressing configuration to two-way interleaved addressing.
Claim 3
Dependent Claim
37 words
The combination as recited in claim 1 wherein said four-way interleaved addressing mode is a normal mode and the two-way interleaved addressing mode is a reconfigured mode and wherein there are two reconfigured modes R1 and R2.
Claim 4
Dependent Claim
54 words
The combination as recited in claim 2 wherein the four memory modules in the normal four-way mode are MMS0, MMS1, MMS2 and MMS3 and wherein reconfigured mode R1 comprises MMS2 and MMS3 occupying a first half of the total addressable space and MMS0 and MMS1 occupying a second half of the total addressable space.
Claim 5
Dependent Claim
38 words
The combination as recited in claim 3 wherein the reconfigured mode R2 comprises MMS0 and MMS1 occuppying the first half of the total addressable space and MMS2 and MMS3 occupying the second half of the total addressable space.
Claim 6
Dependent Claim
53 words
The combination as recited in claim 4 being reconfiguration mode R1 and is utilized when a fault is located in either module MMS2 or MMS3 or in both MMS2 and MMS3, and reconfiguration mode R2 being utilized when a fault located in either module MMS0 or MMS1 or in both MMS0 and MMS1.
Claim 7
Independent Claim
135 words
A method of reconfiguring a computer memory system comprised of four memory modules arranged in a four-way interleaved addressing configuration mode, to a two-way interleaved addressing configuration, said method comprising the steps of: a. generating, in response to first predetermined bits from a first instruction of a program under execution, first reconfiguration signals indicative of a desired predetermined state of interleaved addressing configuration; b. generating, in response to predetermined address bit positions of a second instruction of a program under execution, second reconfiguration signals for addressing any one of said four modules in any one of said two-way interleaved addressing configurations; and, c. applying said first or second reconfiguration signals to said computer memory system to control said computer memory system for varying the four-way interleaved addressing configuration mode to two-way interleaved addressing configuration. >
Claim 8
Independent Claim
135 words
A method of reconfiguring a computer memory system comprised of four memory modules arranged in a four-way interleaved addressing configuration mode, to a two-way interleaved addressing configuration, said method comprising the steps of: a. generating, in response to first predetermined bits from a first instruction of a program under execution, first reconfiguration signals indicative of a desired predetermined state of interleaved addressing configuration; b. generating, in response to predetermined address bit positions of a second instruction of a program under execution, second reconfiguration signals for addressing any one of said four modules in any one of said two-way interleaved addressing configurations; and, c. applying said first or second reconfiguration signals to said computer memory system to control said computer memory system for varying the four-way interleaved addressing configuration mode to two-way interleaved addressing configuration. >
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-11 | 1977-09-10 | 1978-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-11 | 1981-09-10 | 1982-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-11 | 1985-09-10 | 1986-03-12 | $7700.00 | Window Closed / Lapsed |