Patent US3796893A successfully refreshed from Google Patents.
US3796893A
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Peripheral circuitry for dynamic mos rams
Assignee: Motorola Solutions Inc
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Filing: 1972-08-28
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Granted: 1974-03-12
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Expires: 1992-08-28
Abstract
Abstract Improved circuits for a dynamic MOS RAM having a storage array of inverting storage cells, including an improved input buffer, an improved write circuit, and a sense circuit. The input buffer circuit includes a dynamic latch circuit clocked by the first clock complement signal and is compatible with TTL logic levels. The cross coupled gate nodes of the dynamic latch are conditionally discharged by circuitry which includes a ratio type first address inverter, and a second ratio type address inverter followed by a third ratioless inverter, whose output conditionally discharges one of the cross coupled gate nodes of the dynamic latch. A separate write circuit drives each digitsense column bus line, and includes a push-pull driver clocked by the third clock input signal. The pull-up and pull-down field effect transistors of the push-pull driver each have an exclusive OR type circuit for conditionally discharging the precharged gate electrodes of the pull-up and pull-down field effect transistors, depending on the voltages on the data input signal and the data control signal. The ratioless data control inverter and the data input inverter provide the complement signals required by the two exclusive OR type circuits.
Inventors
- 👤 C Hoffman
- 👤 D Kube
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
155 words
An input buffer circuit coupled to first and second power supply terminals, a clock signal terminal, a clock complement signal terminal, an input signal terminal, and including in combination a dynamic latch circuit coupled to the clock complement signal terminal and first and second cross-coupling nodes thereof, the improvement comprising: a first inverter coupled to the input signal terminal, the clock signal terminal, and the first cross-coupling nodes; a second inverter coupled to the clock signal terminal and the input signal terminal, and; a ratioless inverter coupled to the clock signal terminal, the output node of the second inverter and the second crosscoupling node, wherein only one of the first and second crosscoupling nodes may be discharged to the second power supply voltage during a delay between the trailing edge of a clock signal applied to the clock signal terminal and the leading edge of a clock complement signal applied to the clock signal terminal.
Claim 2
Dependent Claim
155 words
An input buffer circuit coupled to first and second power supply terminals, a clock signal terminal, a clock complement signal terminal, an input signal terminal, and including in combination a dynamic latch circuit coupled to the clock complement signal terminal and first and second cross-coupling nodes thereof, the improvement comprising: a first inverter coupled to the input signal terminal, the clock signal terminal, and the first cross-coupling nodes; a second inverter coupled to the clock signal terminal and the input signal terminal, and; a ratioless inverter coupled to the clock signal terminal, the output node of the second inverter and the second crosscoupling node, wherein only one of the first and second crosscoupling nodes may be discharged to the second power supply voltage during a delay between the trailing edge of a clock signal applied to the clock signal terminal and the leading edge of a clock complement signal applied to the clock signal terminal.
Claim 3
Dependent Claim
158 words
The input buffer circuit of claim 1 wherein the dynamic latch includes a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, and a fourth field-effect transistor, the first field-effect transistor having its drain coupled to the clock complement signal Terminal and its source coupled to a first output node and its gate coupled to the second cross-coupling node, the second field-effect transistor having its drain coupled to the first output node and its source coupled to the second power supply terminal and its gate coupled to the first cross-coupling node, the third field-effect transistor having its drain coupled to the clock complement signal terminal and its source coupled to a second output node and its gate coupled to the first cross-coupling node, and the fourth field-effect transistor having its drain coupled to the second output node and its source coupled to the second power supply terminal and its gate coupled to the second cross-coupling node.
Claim 4
Dependent Claim
78 words
The input buffer circuit of claim 1 wherein the first inverter includes first and second field-effect transistors, the fifth field-effect transistor having its drain coupled to the first power supply terminal, its gate coupled to the clock terminal and its source coupled to the first cross-coupling node, the second field-effect transistor having its drain coupled to the first cross-coupling node and its gate coupled to the input terminal and its source coupled to the second power supply terminal.
Claim 5
Dependent Claim
79 words
The input buffer circuit of claim 1 wherein the second inverter includes first and second field-effect transistors, the first field-effect transistor having its drain coupled to the first power supply terminal and its gate coupled to the clock signal terminal and its source coupled to a first node, and the second field-effect transistor having its drain coupled to the first node and its gate coupled to the input signal and its source coupled to the second power supply terminal.
Claim 6
Dependent Claim
80 words
The input buffer circuit of claim 4 wherein the ratioless inverter includes third and fourth field-effect transistors, the third field-effect transistor having its drain coupled to the first power supply terminal and a gate coupled to the clock signal terminal and its source coupled to the second cross-coupling node, and the fourth field-effect transistor having its drain coupled to the second cross-coupling node and its gate coupled to the first node and its source coupled to the second supply terminal.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-11 | 1977-09-10 | 1978-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-11 | 1981-09-10 | 1982-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-11 | 1985-09-10 | 1986-03-12 | $7700.00 | Window Closed / Lapsed |