Multi-level large scale integrated circuit array having standard test points

Claim 2

An integrated circuit interconnection method for interconnecting operable circuits into an electrical function on an integrated circuit wafer having a plurality of operable and inoperable circuits for testing the selected circuits in a uniform manner, the operable and inoperable circuits having random positions in a non-uniform distribution and having primary signal-connect means associated therewith at a first level of wafer metallization, comprising the steps of: preparing a master pattern having predetermined circuit locations defining the positions of operable circuits to be selected from any of the operable circuits irrespective of their position and distribution the predetermined circuit locations corresponding to a standardized pattern of good circuits of all wafers to be similarly processed into the electrical function; testing the plurality of operable and inoperable circuits at the primary signal-connect means to determine positions of operable and inoperable circuits; selecting operable circuits from any of the tested operable circuits irrespective of their position and distribution on the wafer, the number of the selected operable circuits being at least equal to the number of predetermined circuit locations on the master pattern; electrically coupling and routing the primary signal-connect means of each of the selected operable circuits to sites of secondary signal-connect means of each of the selected operable circuits by insulation and metallizing formation and masking processes and thereby terminating each of the selected operable circuits in the secondary signal-connect means and in the positions corresponding to the predetermined circuit locations of the master pattern; selecting electrical coupling test-point means from at least a portion of some of the secondary signal-connect means, the test-point means positioned at test-point locations corresponding to a standardized pattern of test-point means conforming to the positions of probes on electrical testing apparatus; electrically testing the selected operable circuits at the testpoint means utilizing the electrical testing apparatus; and further electrically coupling the wafer circuits from the secondary signal-connect means into the electrical function by use of standard masking means identical to all wafers to be similarly processed into the electrical function.

Claim 3

The method of claim 1 wherein said coupling and testing steps further comprise the steps of: electrically isolating each of the inoperable circuits, including each of the inoperable circuits coinciding with any ones of the predetermined circuit locations, and electrically isolating each of the unselected operable circuits by Deposition of insulation material over the first level of metallization; exposing the primary signal-connect means of the selected operable circuits by masking and insulation material removal means; routing electrical conduction means from the exposed primary signal-connect means to the sites of the secondary signal-connect means, whereby some of the secondary signal-connect means at the predetermined circuit locations are situated at a corresponding number of the inoperable circuits in electrical isolation therefrom; and routing further electrical conduction means from the routed electrical conduction means to the test-point locations.

Claim 4

The method of claim 1 for use with a plurality of wafers, all to be interconnected into the electrical function, further including the steps of: electrically coupling the primary signal-connect means of any ones of the selected operable circuits of each of the wafers to the sites of the secondary signal-connect means and electrically coupling in an identical manner for each of the wafers the secondary signal-connect means thereof by use of the identical masking means into identical circuit configurations corresponding to the electrical function; and electrically coupling the test-point means to the test-point locations corresponding to identical locations of the test-point means of the plurality of wafers.

Claim 5

An integrated circuit interconnection method for interconnecting operable circuits into an electrical function on each of a plurality of integrated circuit wafers and for identically testing the operable circuits, each of the wafers both capable of performing the same electrical function and having a plurality of operable and inoperable circuits in random positions of a non-uniform distribution, each of the operable and inoperable circuits having primary signal-connect means associated therewith in a first level of metallization, comprising the steps of: preparing a master pattern having predetermined circuit locations, for each and every one of the wafers, the master pattern defining identical positions of operable circuits to be selected from any of the operable circuits irrespective of the position and distribution thereof on individual ones of the wafers at a level subsequent to the first level of metallization; testing the plurality of operative and inoperative circuits of each of the wafers at the primary signal-connect means to determine locations of operable and inoperable circuits; for each of the wafers, selecting operable circuits from any of the operable circuits irrespective of the position and distribution thereof on individual ones of the wafers, the number of selected operable circuits at least capable of performing the electrical function, and the number of the selected operable circuits being at least equal to the number of predetermined circuit locations of the master pattern; for each of the wafers, electrically insulating the operable and inoperable circuits and the primary signal-connect means from one another to form a first insulation layer over the circuits and over the primary signal-connect means, with feedthrough means in the first insulation layer opening to the primary signal-connect means of the selected operable circuits; for each of the wafers, electrically coupling and routing the primary signal-connect means of each of the selected operable circuits through the feedthrough means and to sites of secondary signal-connect means of each of the selected operable circuits and thereby terminating each of the selected operable circuits in the identical positions corresponding to the predetermined circuit locations of the master pattern; electrically coupling identically positioned test-points for all the wafers to the secondary signal-connect means at test-point locations; and further identical electrically coupling and routing of each of the plurality of wafers from the secondary signal-connect means of each of the wafers by use of standard mAsking means identical to all of the wafers for interconnecting the selected operable circuits thereof in such a manner as to enable each of the wafers to perform the electrical function.

Claim 6

An integrated circuit interconnection method for interconnecting operable circuits into an electrical function on each of a plurality of integrated circuit wafers and for identically testing the operable circuits, each of the wafers both capable of performing the same electrical function and having a plurality of operable and inoperable circuits in random positions of a non-uniform distribution, each of the operable and inoperable circuits having primary signal-connect means associated therewith in a first level of metallization, comprising the steps of: preparing a master pattern having predetermined circuit locations, for each and every one of the wafers, the master pattern defining identical positions of operable circuits to be selected from any of the operable circuits irrespective of the position and distribution thereof on individual ones of the wafers at a level subsequent to the first level of metallization; testing the plurality of operative and inoperative circuits of each of the wafers at the primary signal-connect means to determine locations of operable and inoperable circuits; for each of the wafers, selecting operable circuits from any of the operable circuits irrespective of the position and distribution thereof on individual ones of the wafers, the number of selected operable circuits at least capable of performing the electrical function, and the number of the selected operable circuits being at least equal to the number of predetermined circuit locations of the master pattern; for each of the wafers, electrically insulating the operable and inoperable circuits and the primary signal-connect means from one another to form a first insulation layer over the circuits and over the primary signal-connect means, with feedthrough means in the first insulation layer opening to the primary signal-connect means of the selected operable circuits; for each of the wafers, electrically coupling and routing the primary signal-connect means of each of the selected operable circuits through the feedthrough means and to sites of secondary signal-connect means of each of the selected operable circuits and thereby terminating each of the selected operable circuits in the identical positions corresponding to the predetermined circuit locations of the master pattern; electrically coupling identically positioned test-points for all the wafers to the secondary signal-connect means at test-point locations; and further identical electrically coupling and routing of each of the plurality of wafers from the secondary signal-connect means of each of the wafers by use of standard mAsking means identical to all of the wafers for interconnecting the selected operable circuits thereof in such a manner as to enable each of the wafers to perform the electrical function.

Claim 7

A method as in claim 4 further including the step of electrically testing the wafers at the test-point locations with a testing machine having a fixed array of probes corresponding in position to the test-point locations.