Data processing memory system with bidirectional data bus

Claim 1

A digital computer memory system for use with a central processing unit having combined input-output means, said memory system comprising a memory unit having a first input means for receiving digital information to be stored therein and a first output means for transmitting digital information already stored therein, a bidirectional latch unit having a second input means, a second output means, and a combined input-output means, a first transmitting means connecting said second output means of said bidirectional latch unit to said first input means of said memory unit for transmitting information thereto during a WRITE operation, a second transmitting means connecting said first output means of said memory unit to said second input means of said bidirectional latch unit for transmitting information stored in said memory unit to said bidirectional latch unit during a READ operation, and a bidirectional data bus interconnecting said combined inputoutput means of said bidirectional latch unit and said combined input-output means of said central processing unit for transmitting information between said bidirectional latch unit and said central processing unit in both directions, said bidirectional latch unit comprising means connecting said combined input-output means thereof to said second output means for transmitting information from said central processing unit to said memory unit for storage by the latter during a WRITE operation, said bidirectional latch unit comprising means for maintaining on the data bus after said WRITE operation the integrity of the information previously transmitted by said first transmitting means to said first input means of said memory unit during said WRITE operation, whereby the central processing unit may check said stored information for errors.