US3795860A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Network tester employing latched test switching units
Assignee: Teradyne Inc
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Filing: 1972-07-13
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Granted: 1974-03-05
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Expires: 1992-07-13
Abstract
Abstract The testing apparatus disclosed herein is adapted to test backplane wiring so as to determine if all desired connections exist and whether any undesired connections may be present. Such backplanes typically comprise a multiplicity of terminal points which may be interconnected in arbitrary manner to form a plurality of networks of connected points. The tester employs an addressable switching and memory unit for each terminal point. When addressed, each point is first connected to a first bus and, when the addressing is terminated, is thereafter connected to a second bus, this second connection being maintained under the control of the memory or latch associated with each switching unit. Prior to being addressed, each point is in effect isolated by the switching unit and allowed to float in potential. As the successive points in a given network are addressed, the system tests for continuity between the first and second buses to determine if the desired connections exist. After all terminal points which should be in the selected network have been latched into connection with the second bus, all remaining points are commonly switched into connection with the first bus. Testing for isolation at this time determines whether any undesired connections affecting the selected network are present.
Inventors
- 👤 T Sylvan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 13:29
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/50; G01R31/66; G01R31/67
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
253 words
A system for testing interconnections in a matrix of terminal points, said system comprising a plurality of continuity test switching units, one for each point, and a decoding network permitting each unit to be selectively addressed by means of coded selection signals, each of said testing units including a latch element which is set when the unit is addressed and a semiconductor switching means, said switching means being operative, during addressing of the unit, to connect the respective terminal point to a first bus which is common to all of said units and being operative, after termination of addressing and whiLe said latch element is set, to connect the respective terminal point to a second bus also common to all of said units, whereby continuity in an interconnection network can be determined by testing for continuity between said first and second buses while sequentially addressing the test switching units corresponding to the points in the network, each latch element being resettable by a common reset signal to place said switching means in an initial state in which said terminal point is isolated from both of said buses, said switching means being responsive, while in said initial state, to a gate signal, common to a plurality of said units, for connecting the respective terminal point to said first bus, whereby isolation of a network previously addressed can be determined by applying said common gate signal to connect all remaining points to said first bus while testing for isolation between said first and second buses.
Claim 2
Independent Claim
253 words
A system for testing interconnections in a matrix of terminal points, said system comprising a plurality of continuity test switching units, one for each point, and a decoding network permitting each unit to be selectively addressed by means of coded selection signals, each of said testing units including a latch element which is set when the unit is addressed and a semiconductor switching means, said switching means being operative, during addressing of the unit, to connect the respective terminal point to a first bus which is common to all of said units and being operative, after termination of addressing and whiLe said latch element is set, to connect the respective terminal point to a second bus also common to all of said units, whereby continuity in an interconnection network can be determined by testing for continuity between said first and second buses while sequentially addressing the test switching units corresponding to the points in the network, each latch element being resettable by a common reset signal to place said switching means in an initial state in which said terminal point is isolated from both of said buses, said switching means being responsive, while in said initial state, to a gate signal, common to a plurality of said units, for connecting the respective terminal point to said first bus, whereby isolation of a network previously addressed can be determined by applying said common gate signal to connect all remaining points to said first bus while testing for isolation between said first and second buses.
Claim 3
Dependent Claim
18 words
A system as set forth in claim 1 wherein said switching means comprises complementary conductivity type, field-effect transistors.
Claim 4
Dependent Claim
49 words
A system as set forth in claim 1 wherein said decoding network and said latch element comprise C-MOS field-effect transistor logic elements, said switching means comprises complementary conductivity type, MOS field-effect transistors, and said first and second buses are the supply buses for said logic elements and said transistors.
Claim 5
Dependent Claim
22 words
A system as set forth in claim 3 wherein said latch element comprises a flip-flop including a pair of interconnected NOR gates.
Claim 6
Independent Claim
232 words
A system for testing interconnections in a matrix of terminal points, said system comprising a plurality of test switching units, one for each point, and a decoding network permitting each unit to be selectively addressed by means of coded selection signals, each of said testing units being operative, when addressed, to connect the respective point to a first bus, which first bus is common to all of said testing units, each of said testing units being also operative, after termination of addressing thereof, to latch the respective terminal point into connection with a second bus, also common to all of said testing means, whereby continuity in an interconnection network can be determined by testing for continuity between said first and second buses while sequentially addressing the test switching units corresponding to the points in the network, each unit being resettable, by a reset signal applied commonly to all said units, to an initial state in which the respective terminal is isolated from both buses, each unit, while in its reset condition, being responsive to a gate signal commonly applied to a plurality of said test switching units for connecting the respective terminal point to said first bus, whereby isolation of a network previously addressed can be determined by applying said common gage signal to connect all remaining points to said first bus while testing for isolation between said first and second buses.
Claim 7
Independent Claim
232 words
A system for testing interconnections in a matrix of terminal points, said system comprising a plurality of test switching units, one for each point, and a decoding network permitting each unit to be selectively addressed by means of coded selection signals, each of said testing units being operative, when addressed, to connect the respective point to a first bus, which first bus is common to all of said testing units, each of said testing units being also operative, after termination of addressing thereof, to latch the respective terminal point into connection with a second bus, also common to all of said testing means, whereby continuity in an interconnection network can be determined by testing for continuity between said first and second buses while sequentially addressing the test switching units corresponding to the points in the network, each unit being resettable, by a reset signal applied commonly to all said units, to an initial state in which the respective terminal is isolated from both buses, each unit, while in its reset condition, being responsive to a gate signal commonly applied to a plurality of said test switching units for connecting the respective terminal point to said first bus, whereby isolation of a network previously addressed can be determined by applying said common gage signal to connect all remaining points to said first bus while testing for isolation between said first and second buses.
Claim 8
Independent Claim
229 words
A system for testing interconnections in a matrix of terminal points, said system comprising a plurality of continuity test switching units, one for each point, and a decoding network permitting each unit to be selectively addressed by means of coded selection signals, each of said testing units being operative, when addressed, to connect the respective point to a first bus, which first bus is common to all of said testing units, each of said testing units being also operative, after termination of addressing thereof, to connect the respective terminal point to a second bus, also common to all of said testing means, whereby continuity in an interconnection network can be determined by testing for continuity between said first and second buses while sequentially addressing the test switching units corresponding to the points in the network, said system including also a plurality of isolation test switching means, one for each terminal point, said isolation test switching means being responsive to a gate signal commonly applied to all of said isolation test switching means for connecting any terminal points not then connected to said second bus to said first bus in response to said gate signal, whereby isolation of a network previously addressed can be determined by applying said common gate signal to connect all remaining points to said first bus while testing for isolation between said first and second buses.
Claim 9
Independent Claim
229 words
A system for testing interconnections in a matrix of terminal points, said system comprising a plurality of continuity test switching units, one for each point, and a decoding network permitting each unit to be selectively addressed by means of coded selection signals, each of said testing units being operative, when addressed, to connect the respective point to a first bus, which first bus is common to all of said testing units, each of said testing units being also operative, after termination of addressing thereof, to connect the respective terminal point to a second bus, also common to all of said testing means, whereby continuity in an interconnection network can be determined by testing for continuity between said first and second buses while sequentially addressing the test switching units corresponding to the points in the network, said system including also a plurality of isolation test switching means, one for each terminal point, said isolation test switching means being responsive to a gate signal commonly applied to all of said isolation test switching means for connecting any terminal points not then connected to said second bus to said first bus in response to said gate signal, whereby isolation of a network previously addressed can be determined by applying said common gate signal to connect all remaining points to said first bus while testing for isolation between said first and second buses.
Claim 10
Dependent Claim
91 words
A system as set forth in claim 6 wherein each continuity switching unit includes a MOS field-effect transistor of one conductivity type connecting the respective point to said first bus and a MOS field-effect transistor of the opposite conductivity type connecting the respective point to said second type and wherein said isolation test switching means comprises a pair of MOS field-effect transistors of said one conductivity type connected in series to form a conduction path between the respective point and said first bus in parallel with the first said field-effect transistor.
Claim 11
Dependent Claim
396 words
A wiring test system for testing a matrix of connection points interconnected in an arbitrary plurality of networks, said system comprising a multiplicity of switching units all energized from a common pair of supply buses, one unit for each of said points, each unit comprising: a first FET of one conductivity type connecting the respective point to a first of said supply buses; second and third FETs of said first conductivity type, said second and third FETs being connected in series with other, with the series pair thereby formed being in parallel with said first FET; a FET of conductivity type complementary to said first type connecting the respective point to the other supply bus; a COS/MOS flip-flop having a set state and a reset state; means for applying to said first FET a respective select signal provided to the unit to rendering said first FET conductive, said select signal being applied also to said flip-flop for placing it in its set state; COS/MOS gate means responsive to said select signal and interconnecting said flip-flop and said complementary type FET for permitting said complementary type FET to be rendered conductive by said flip-flop in the set state after termination of said select signal, said third FET being interconnected so that said third FET is rendered non-conductive when said flip-flop is in its set state and conductive when said flip-flop is in its reset state; means for applying a gate signal, common to all of said units, directly to the gate terminal of said second FET, whereby conduction between said point and said first bus can be developed progressively by a gradually changing gate signal when said flip-flop is in its reset state; and means for applying a reset signal, common to all of said units, to said flip-flop for placing it in its reset state, said test system comprising also COS/MOS decoding means permitting individual ones of said switching units to be selected by coded address signals applied commonly to said units, whereby continuity in a desired network can be tested by sequentially addressing the switching units corresponding to the point properly in the network while testing for continuity between said supply buses and isolation of said network can be tested by applying a progressively changing gate signal commonly to the second said FET in each unit while testing for essential isolation between said supply buses.
Claim 12
Dependent Claim
396 words
A wiring test system for testing a matrix of connection points interconnected in an arbitrary plurality of networks, said system comprising a multiplicity of switching units all energized from a common pair of supply buses, one unit for each of said points, each unit comprising: a first FET of one conductivity type connecting the respective point to a first of said supply buses; second and third FETs of said first conductivity type, said second and third FETs being connected in series with other, with the series pair thereby formed being in parallel with said first FET; a FET of conductivity type complementary to said first type connecting the respective point to the other supply bus; a COS/MOS flip-flop having a set state and a reset state; means for applying to said first FET a respective select signal provided to the unit to rendering said first FET conductive, said select signal being applied also to said flip-flop for placing it in its set state; COS/MOS gate means responsive to said select signal and interconnecting said flip-flop and said complementary type FET for permitting said complementary type FET to be rendered conductive by said flip-flop in the set state after termination of said select signal, said third FET being interconnected so that said third FET is rendered non-conductive when said flip-flop is in its set state and conductive when said flip-flop is in its reset state; means for applying a gate signal, common to all of said units, directly to the gate terminal of said second FET, whereby conduction between said point and said first bus can be developed progressively by a gradually changing gate signal when said flip-flop is in its reset state; and means for applying a reset signal, common to all of said units, to said flip-flop for placing it in its reset state, said test system comprising also COS/MOS decoding means permitting individual ones of said switching units to be selected by coded address signals applied commonly to said units, whereby continuity in a desired network can be tested by sequentially addressing the switching units corresponding to the point properly in the network while testing for continuity between said supply buses and isolation of said network can be tested by applying a progressively changing gate signal commonly to the second said FET in each unit while testing for essential isolation between said supply buses.
Claim 13
Independent Claim
151 words
The method of testing for a desired interconnection of a matrix of terminal points establishing a plurality of networks, said method comprising for each network in sequence the steps of: sequentially connecting each point in the network under test first to a first, single conductor bus and then to a second, single conductor bus, previous points in each network being maintained in connection with said second bus during connection of subsequent points in the same network to said first bus; during connection of each point in turn to said first bus, testinG for continuity between said first bus and said second bus; after all points in the selected network under test are connected to said second bus, connecting all other points in said matrix simultaneously to said first bus; and during connection of said other points to said first bus, testing for isolation between said first bus and said second bus.
Claim 14
Independent Claim
151 words
The method of testing for a desired interconnection of a matrix of terminal points establishing a plurality of networks, said method comprising for each network in sequence the steps of: sequentially connecting each point in the network under test first to a first, single conductor bus and then to a second, single conductor bus, previous points in each network being maintained in connection with said second bus during connection of subsequent points in the same network to said first bus; during connection of each point in turn to said first bus, testinG for continuity between said first bus and said second bus; after all points in the selected network under test are connected to said second bus, connecting all other points in said matrix simultaneously to said first bus; and during connection of said other points to said first bus, testing for isolation between said first bus and said second bus.
Claim 15
Independent Claim
144 words
The method of testing for a desired interconnection of a matrix of terminal points establishing a plurality of networks, said method comprising for each network in sequence the steps of: in sequence for each point in the network, connecting that point first to a first, single conductor bus and then latching that point into connection with a second, single conductor bus; during connection of each point in turn to said first bus, testing for continuity between said first bus and said second bus; after all points in the network under test are connected to said second bus, connecting all other points in said matrix simultaneously to said first bus; during connection of said other points to said first bus, testing for isolation between said first bus and said second bus; and then delatching all points from either bus before proceeding to the next network.
Claim 16
Independent Claim
144 words
The method of testing for a desired interconnection of a matrix of terminal points establishing a plurality of networks, said method comprising for each network in sequence the steps of: in sequence for each point in the network, connecting that point first to a first, single conductor bus and then latching that point into connection with a second, single conductor bus; during connection of each point in turn to said first bus, testing for continuity between said first bus and said second bus; after all points in the network under test are connected to said second bus, connecting all other points in said matrix simultaneously to said first bus; during connection of said other points to said first bus, testing for isolation between said first bus and said second bus; and then delatching all points from either bus before proceeding to the next network.
Claim 17
Independent Claim
182 words
The method of operating a test system comprising a plurality of test switching units, one for each terminal point in a wiring matrix to be tested, each testing unit being operative, when addressed, to connect the respective point to a first bus, which first bus is common to all of said testing units, and operative, after termination of addressing, to connect the respective terminal point to a second bus, also common to all of said switching units, each unit including also an isolation test means responsive to a common gate signal for connecting the respective terminal point to said first bus in response to said gate signal, said method comprising: addressing sequentially the units corresponding to the points in a preselected network to be tested and simultaneously disabling the respective isolation test means in each addressed unit; testing for continuity between said first bus and said second bus as each unit is addressed; applying a gate signal commonly to all said test units; and during the application of said gate signal, testing for isolation between said first bus and said second bus.
Claim 18
Independent Claim
182 words
The method of operating a test system comprising a plurality of test switching units, one for each terminal point in a wiring matrix to be tested, each testing unit being operative, when addressed, to connect the respective point to a first bus, which first bus is common to all of said testing units, and operative, after termination of addressing, to connect the respective terminal point to a second bus, also common to all of said switching units, each unit including also an isolation test means responsive to a common gate signal for connecting the respective terminal point to said first bus in response to said gate signal, said method comprising: addressing sequentially the units corresponding to the points in a preselected network to be tested and simultaneously disabling the respective isolation test means in each addressed unit; testing for continuity between said first bus and said second bus as each unit is addressed; applying a gate signal commonly to all said test units; and during the application of said gate signal, testing for isolation between said first bus and said second bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-04 | 1977-09-03 | 1978-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-04 | 1981-09-03 | 1982-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-04 | 1985-09-03 | 1986-03-05 | $7700.00 | Window Closed / Lapsed |