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US3795772A Expired / Lapsed US ⏱️ 0.0 years remaining

Synchronization system for pulse orthogonal multiplexing systems

Assignee: United States Department of the Navy
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Filing: 1972-05-01
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Granted: 1974-03-05
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Expires: 1992-05-01
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Abstract

Abstract A synchronization system having a plurality of control loops operative together to optimize the rate of frequency acquisition and synchronization. A first loop acquires the frequency of the unknown signal. A coarse phase-lock loop then adjusts the system to provide a phase-error signal. A fine phase-lock loop then makes the final adjustments to the system. As each step in the synchronization sequence is achieved, the circuitry which is no longer needed is switched out of operation.

Inventors

  • 👤 E Hill
  • 👤 H Mansnerus

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 22:17
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/087; H03L7/10; H03L7/107; H03L7/1075; H04; H04B; H04B1/00; H04B1/69; H04B1/707; H04L; H04L23/00; H04L23/02

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 430 words
A synchronization system for synchronizing the demultiplexer of a pulse orthogonal multiplexing system in both frequency and phase with respect to the received signals from the multiplexer, comprising: a. a system input to which signals from the multiplexer are fed; b. a voltage controlled oscillator which is controlled in frequency and phase to provide a reference frequency to be phase locked with the multiplexer; c. a demultiplexer waveform generator connected to the output of said voltage controlled oscillator for generating synchronization waveform signals used for phase locking with input signal waveforms from the multiplexer; d. an active loop filter which includes loop filter portions for frequency acquisition, coarse phase-lock and fine phase-lock, respectively; e. first, sEcond, third and fourth multipliers, each of which derive a d.c. voltage as a function of the phase angle between the input signals from the multiplexer and respective synchronization waveform signals from the demultiplexer waveform generator; f. frequency acquisition phase-lock circuitry which includes a first switch means operable to be connected between said system input and the input of said voltage controlled oscillator via the frequency acquisition portion of said active loop filter for controlling said oscillator upon actuation of said first switch means, said first multiplier output operating to actuate said first switch means; g. coarse phase-lock circuitry which includes said second multiplier and a second switch means connected between said system input and the input of said voltage controlled oscillator via the coarse phase-lock portion of said active loop filter, also for controlling said oscillator and operable to be disconnected upon actuation of said second switch means; said fourth multiplier output operating to actuate said second switch means; h. fine phase-lock circuitry which includes said third multiplier connected between said system input and the input of said voltage controlled oscillator via the fine phase-lock portion of said active loop filter also for controlling said oscillator; i. select synchronization subcarrier waveforms from said demultiplexer waveform generator being used to actuate said first, second, third and fourth multipliers, respectively; j. said frequency acquisition phase-lock circuitry initially acquiring the frequency of an unknown incoming signal received from the multiplexer at said system input; k. said coarse phase-lock circuitry providing a phase-error signal to reduce phase error; l. said fine phase-lock circuitry providing final synchronization adjustment; m. said frequency acquisition and coarse phase-lock circuits being sequentially switched out of operation by said first and said second switch means, respectively, as each step in synchronization is achieved wherein continuous monitoring of the synchronization status and exclusion or inclusion of error signals is automatically achieved to optimize synchronization performance.
Claim 2
Dependent Claim 430 words
A synchronization system for synchronizing the demultiplexer of a pulse orthogonal multiplexing system in both frequency and phase with respect to the received signals from the multiplexer, comprising: a. a system input to which signals from the multiplexer are fed; b. a voltage controlled oscillator which is controlled in frequency and phase to provide a reference frequency to be phase locked with the multiplexer; c. a demultiplexer waveform generator connected to the output of said voltage controlled oscillator for generating synchronization waveform signals used for phase locking with input signal waveforms from the multiplexer; d. an active loop filter which includes loop filter portions for frequency acquisition, coarse phase-lock and fine phase-lock, respectively; e. first, sEcond, third and fourth multipliers, each of which derive a d.c. voltage as a function of the phase angle between the input signals from the multiplexer and respective synchronization waveform signals from the demultiplexer waveform generator; f. frequency acquisition phase-lock circuitry which includes a first switch means operable to be connected between said system input and the input of said voltage controlled oscillator via the frequency acquisition portion of said active loop filter for controlling said oscillator upon actuation of said first switch means, said first multiplier output operating to actuate said first switch means; g. coarse phase-lock circuitry which includes said second multiplier and a second switch means connected between said system input and the input of said voltage controlled oscillator via the coarse phase-lock portion of said active loop filter, also for controlling said oscillator and operable to be disconnected upon actuation of said second switch means; said fourth multiplier output operating to actuate said second switch means; h. fine phase-lock circuitry which includes said third multiplier connected between said system input and the input of said voltage controlled oscillator via the fine phase-lock portion of said active loop filter also for controlling said oscillator; i. select synchronization subcarrier waveforms from said demultiplexer waveform generator being used to actuate said first, second, third and fourth multipliers, respectively; j. said frequency acquisition phase-lock circuitry initially acquiring the frequency of an unknown incoming signal received from the multiplexer at said system input; k. said coarse phase-lock circuitry providing a phase-error signal to reduce phase error; l. said fine phase-lock circuitry providing final synchronization adjustment; m. said frequency acquisition and coarse phase-lock circuits being sequentially switched out of operation by said first and said second switch means, respectively, as each step in synchronization is achieved wherein continuous monitoring of the synchronization status and exclusion or inclusion of error signals is automatically achieved to optimize synchronization performance.
Claim 3
Dependent Claim 54 words
A system as in claim 1 wherein said frequency acquisition phase-lock circuitry includes a band pass filter, a zero crossing detector and a flip-flop circuit, respectively, connected in series, the input to said band pass filter connected to the system input and the output of said flip-flop circuit connected to said first switch means.
Claim 4
Dependent Claim 68 words
A system as in claim 1 wherein a network comprising a dual time constant RC peak detector circuit connected in series between a low pass filter and a threshold detector is used in said second switch means with said coarse phase-lock circuitry to enhance the probability of in-synchronization detection over false alarm occurrence and prevent false closure of said second switch means once fine phase lock is achieved.

References Cited (Backward Citations)

US3032720A Cited
US3204034A Cited
US3421105A Cited
US3578956A Cited
US3585298A Cited
US3691474A Cited
US3703686A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-03-04 1977-09-03 1978-03-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-03-04 1981-09-03 1982-03-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-03-04 1985-09-03 1986-03-05 $7700.00 Window Closed / Lapsed

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