US3794854A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal sensing and storage circuit
Assignee: RCA Corp
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Filing: 1972-11-30
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Granted: 1974-02-26
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Expires: 1992-11-30
Abstract
Abstract Circuit for distinguishing signals of relatively long duration (information) on a plurality of input lines from one or more signals of relatively short duration (noise) on these same lines. Any signal present on a line enables a gate for that line which is normally maintained in a primed state by a storage element connected to that line. The enabled gate causes a circuit which is common to all lines to produce a delayed pulse. If, when the delayed pulse occurs, a normally primed gate for a line is still enabled, the storage element of that line is set and the latter disables that gate. If, on the other hand, the normally primed gate is not enabled when the delayed pulse occurs, the storage element is not disturbed and the gate is retained in its primed condition.
Inventors
- 👤 R Hanson
- 👤 H Fineman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:50
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
141 words
In combination: a plurality of circuits, each including: a. a two state storage means; b. logic gate means normally primed by the storage means; and c. a signal input line coupled to an input terminal of said logic gate means for enabling the latter in response to a signal on said line: pulse producing means common to said plurality of circuits coupled to the output terminal of all of said logic gate means for producing a delayed output pulse in response to a signal from any logic gate means; and means responsive to the presence of a signal on an input line at the time a delayed pulse is produced by said pulse producing means for changing the state of the storage means associated with that input line, thereby disabling the logic gate means to which said input line is coupled.
Claim 2
Dependent Claim
141 words
In combination: a plurality of circuits, each including: a. a two state storage means; b. logic gate means normally primed by the storage means; and c. a signal input line coupled to an input terminal of said logic gate means for enabling the latter in response to a signal on said line: pulse producing means common to said plurality of circuits coupled to the output terminal of all of said logic gate means for producing a delayed output pulse in response to a signal from any logic gate means; and means responsive to the presence of a signal on an input line at the time a delayed pulse is produced by said pulse producing means for changing the state of the storage means associated with that input line, thereby disabling the logic gate means to which said input line is coupled.
Claim 3
Dependent Claim
43 words
In the combination as set forth in claim 1, said pulse producing means comprising means for producing a pulse delayed an interval Delta T after the last occurring of a group of successive signals spaced intervals less than Delta T from one another.
Claim 4
Dependent Claim
41 words
In the combination as set forth in claim 1, said last-named means comprising, in each circuit, second logic gate means receptive both of the delayed pulse and of the output signal produced by the first mentioned gate means of that circuit.
Claim 5
Dependent Claim
19 words
In the combination as set forth in claim 1, said logic gate means comprising metal-oxide semiconductor transmission gate means.
Claim 6
Dependent Claim
16 words
In the combination as set forth in claim 1, said storage means comprising a set-reset flip-flop.
Claim 7
Dependent Claim
16 words
In the combination as set forth in claim 1, said storage circuit comprising a JK flip-flop.
Claim 8
Dependent Claim
46 words
In the combination as set forth in claim 6, said means responsive to the presence of a signal on the input line comprising one of the J and K terminals of said flip-flop and said delayed pulse being applied to the clock terminal of said flip-flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-25 | 1977-08-27 | 1978-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-25 | 1981-08-27 | 1982-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-25 | 1985-08-27 | 1986-02-26 | $7700.00 | Window Closed / Lapsed |