Data communication transmitter utilizing vector waveform generation

Claim 2

A data communication transmitter utilizing a vector waveform generator for simultaneously generating a desired signaling waveform and performing a desired modulation process for transmission over a communication channel in response to a data signal input and comprising frequency source means for generating a data clock signal, a carrier frequency signal and a shift register clock signal, the carrier signal having four components consisting of a first carrier function voltage, a second carrier function voltage of the same frequency as the first carrier function voltage and in quadrature phase relationship therewith, a third carrier function voltage of the same frequency as the first carrier function voltage and in 180* phase relationship therewith, and a fourth carrier function voltage of the same frequency as the second carrier function voltage and in 180* phase relationship therewith, vector waveform generating means comprising electrical conductor means selectively supplied with said four voltage components of the carrier signal, a plurality of first resistor means each connected across a pair of said electrical conductor means, each first resistor means provided with a tap point at which is developed a weighted sum of the selected voltage components of the carrier signal thereby providing a controlled phasing or vector rotation of the resultant carrier frequency voltage signal, a like plurality of second resistor means having first ends thereof adapted to be sequentially electrically connected to the tap points of associated said first resistor means and having second ends connected to a current summing means, digital control means for producing a train of contiguous equal duration pulses in response to a single data signal applied to a data signal input of said digital control means, the duration of each pulse determined by the frequency of the clock signal applied to a clock input of said digital control means, a like plurality of switch means operatively responsive to outputs of said digital control means for sequentially electrically connecting the first end of each of said second resistor means to the tap point of the associated first resistor means, the train of contiguous pulses determining the sequence and equal time periods of the nonoverlapping closed and resistor connecting states of said switch means thereby providing amplitude weighting of a like plurality of resultant sequentially generated phase controlled carrier current signal samples forming a desired signaling waveform in modulated form, and current summing means connected to the second ends of said second resistor means for summing the sequentially generated amplitude and phase controlled carrier current signal samples for transmission over a communication channel in response to the single data signal applied to the data signal input of said digital control means.

Claim 3

The data communication transmitter set forth in claim 1 wherein said frequency source means comprises an oscillator and digital logic means connected to an output of said oscillator for deriving the data clock, carrier frequency and shift register clock signals in digital form, the first carrier function voltage is a first waveform of a square wave type, the second carrier function voltage is a second square wave Of the same frequency as the first square wave and in 90* phase lagging relationship therewith, the third carier function voltage is a third square wave of the same frequency as the first square wave and in 180* phase relationship therewith, and the fourth carrier function voltage is a fourth square wave of the same frequency as the first square wave and in 270* phase lagging relationship therewith.

Claim 4

The data communication transmitter set forth in claim 1 wherein said frequency source means comprises an oscillator for generating sinusoidal shape waveforms, the first carrier function voltage is a first sinuosidal wave cos omega ct, the second carrier function voltage is a second sinusoidal wave sin omega ct, the third carrier function voltage is a third sinusoidal wave -cos omega ct, and the fourth carrier function voltage is a fourth sinusoidal wave -sin omega ct.

Claim 5

The data communication transmitter set forth in claim 1 wherein said electrical conductor means consists of four electrical conductors respectively supplied with the four carrier function voltages to thereby produce the desired signal waveform in single side band modulated form at the output of the transmitter wherein the lower side band is transmitted.

Claim 6

The data communication transmitter set forth in claim 4 wherein the carrier function voltages supplied to the second and fourth of said four conductors are reversed in order to thereby produce the desired signaling waveform in single side band modulated form at the transmitter output wherein the upper side band is transmitted.

Claim 7

The data communication transmitter set forth in claim 4 wherein first ends of said first resistor means are connected selectively to the two electrical conductors supplied with the first and third carrier function voltages, second ends of said first resistor means connected selectively to the two other electrical conductors supplied with the second and fourth carrier function voltages for developing at the tap points the phase controlled resultant carrier voltage signal which is phase controllable over the entire 360* in accordance with the selection of the carrier function voltages supplied to the four electrical conductors.

Claim 8

The data communication transmitter set forth in claim 1 wherein said digital control means is a multi-stage shift register having a like plurality of outputs connected to said switch means whereby the train of contiguous pulses appearing sequentially at the shift register outputs determine the sequence and time periods of the closed states of said switch means, the clock input of said shift register supplied with the shift register clock signal.

Claim 9

The data communication transmitter set forth in claim 7 wherein said switch means are switching transistors having gate electrodes connected respectively to the outputs of said multi-stage shift register.

Claim 10

The data communication transmitter set forth in claim 8 wherein said switching transistors are of the MOSFET type.

Claim 11

The data communication transmitter set forth in claim 1 wherein said digital control means is a multi-stage shift register having a plurality of outputs of number equal to the plurality of said switch means divided by an integer which represents the ratio of shift register to data clock frequencies, the clock input of said shift register supplied with the data clock signal, a plurality of logic AND gates of number equal to the plurality of said switch means and arranged in groups of the number corresponding to the ratio of shift register to data clock frequencies, the groups of AND gates having first inputs respectively connected to the outputs of said shift register whereby each group has its first inputs connected to a common shift register output and having second inputs sequentially addressed to provide the desired sequential operation of said switch means, and digital clock meaNs having an input supplied with the shift register clock signal for cycling at the shift register clock frequency a single output pulse at a plurality of outputs thereof of number equal to the ratio of shift register to data clock frequencies, outputs of said cycling means connected respectively to the second inputs of said AND gates in each group thereof, output of said AND gates connected respectively to said switch means whereby simultaneous inputs to one of said AND gates in a group thereof from an associated shift register output and cycling means output determines the particular switch means in each group of switch means associated with the corresponding group of AND gates which will be operatively responsive for electrically connecting the first end of a particular one of said second resistor means to the tap point of the associated first resistor means.

Claim 12

A data communication transmitter utilizing a vector waveform generator for simultaneously generating a desired signaling waveform and performing a desired modulation process for transmission over a communication channel in response to a data signal input and comprising frequency source means for generating a data clock signal, a carrier frequency signal and a shift register clock signal, the carrier signal having three voltage components consisting of first and second carrier function voltages respectively consisting of a positive and negative D.C. reference voltage and a third component being zero volts, vector waveform generating means comprising three electrical conductors respectively supplied with the three voltage components of the carrier signal, a plurality of first resistor means having first ends connected selectively to the two electrical conductors supplied with the first and second carrier function voltages, second ends of said first resistor means connected to the third electrical conductor supplied with the third component of zero volts, each first resistor means provided with a tap point at which is developed a weighted sum of the selected voltage components of the carrier signal thereby providing a controlled phasing or vector rotation of the resultant carrier frequency voltage signal, a like plurality of second resistor means having first ends thereof adapted to be sequentially electrically connected to the tap points of associated said first resistor means and having second ends connected to a current summing means, digital control means for producing a train of contiguous equal duration pulses in response to a single data signal applied to a data signal input of said digital control means, the duration of each pulse determined by the frequency of the clock signal supplied to a clock input of said digital control means, a like plurality of switch means operatively responsive to outputs of said digital control means for sequentially electrically connecting the first end of each of said second resistor means to the tap point of the associated first resistor means, the train of contiguous pulses determining the sequence and equal time periods of the nonoverlapping closed and resistor connecting states of said switch means thereby providing amplitude weighting of a like plurality of resultant sequentially generated phase controlled carrier current signal samples forming a desired signaling waveform in baseband form at the output of the transmitter, and current summing means connected to the second ends of said second resistor means for summing the sequentially generated amplitude and phase controlled carrier current signal samples for transmission over a communication channel in response to the single data signal applied to the data signal input of said digital control means.

Claim 13

A data communication transmitter utilizing a vector waveform generator for simultaneously generating a desired signaling waveform and performing a desired modulation process for transmission over a communication channel in response to a data signal input and comprising frequency source means for generating a data clock signal, a carrier frequency signal and a shift register clock signal, the carrier signal having three voltage components consisting of first and second carrier function voltages respectively consisting of a positive and negative D.C. reference voltage and a third component being zero volts, vector waveform generating means comprising three electrical conductors respectively supplied with the three voltage components of the carrier signal, a plurality of first resistor means having first ends connected selectively to the two electrical conductors supplied with the first and second carrier function voltages, second ends of said first resistor means connected to the third electrical conductor supplied with the third component of zero volts, each first resistor means provided with a tap point at which is developed a weighted sum of the selected voltage components of the carrier signal thereby providing a controlled phasing or vector rotation of the resultant carrier frequency voltage signal, a like plurality of second resistor means having first ends thereof adapted to be sequentially electrically connected to the tap points of associated said first resistor means and having second ends connected to a current summing means, digital control means for producing a train of contiguous equal duration pulses in response to a single data signal applied to a data signal input of said digital control means, the duration of each pulse determined by the frequency of the clock signal supplied to a clock input of said digital control means, a like plurality of switch means operatively responsive to outputs of said digital control means for sequentially electrically connecting the first end of each of said second resistor means to the tap point of the associated first resistor means, the train of contiguous pulses determining the sequence and equal time periods of the nonoverlapping closed and resistor connecting states of said switch means thereby providing amplitude weighting of a like plurality of resultant sequentially generated phase controlled carrier current signal samples forming a desired signaling waveform in baseband form at the output of the transmitter, and current summing means connected to the second ends of said second resistor means for summing the sequentially generated amplitude and phase controlled carrier current signal samples for transmission over a communication channel in response to the single data signal applied to the data signal input of said digital control means.

Claim 14

A data communication transmitter utilizing a vector waveform generator for simultaneously generating a desired signaling waveform and performing a desired modulation process for transmission over a communication channel in response to a data signal input and comprising frequency source means for generating a data clock signal, a carrier frequency signal and a shift register clock signal, the carrier signal having three voltage components consisting of a first carrier function voltage, a second carrier function voltage of the same frequency as the first carrier function voltage and in 180* phase relationship therewith, and a third component being zero volts, vector waveform generating means comprising three electrical conductors respectively supplied with the three voltage components of the carrier signal, a plurality of first resistor means having first ends connected selectively to the two electrical conductors supplied with the first and second carrier function voltages, second ends of said first resistor means connected to the third electrical conductor supplied with the third component of zero volts, each first resistor means provided with a tap point at which is developed a weighted sum of the selected voltage components of the carrier signal thereby providing a controlled phasing or vector rotation of the resultant carrier frequency voltage signal, a like plurality of second resistor means having first ends thereof adapted to be sequentially electrically connected to the tap points of associated said first resistor means and having second ends connected to a current summing means, digital control means for producing a train of contiguous equal duration pulses in response to a single data signal applied to a data signal input of said digital control means, the duration of each pulse determined by the frequency of the clock signal applied to a clock input of said digital control means, a like plurality of switch means operatively responsive to outputs of said digital control means for sequentially electrically connecting the first end of each of said second resistor means to the tap point of the associated first resistor means, the train of contiguous pulses determining the sequence and periods time periods of the nonoverlapping closed and resistor connecting states of said switch means thereby providing amplitude weighting of a like plurality of resultant sequentially generated phase controlled carrier current signal samples forming a desired signaling waveform in double side band modulated form at the output of the transmitter, and current summing means connected to the second ends of said second resistor means for summing the sequentially generated amplitude and phase controlled carrier current signal samples for transmission over a communication channel in response to the single data signal applied to the data signal input of said digital control means.

Claim 15

A data communication transmitter utilizing a vector waveform generator for simultaneously generating a desired signaling waveform and performing a desired modulation process for transmission over a communication channel in response to a data signal input and comprising frequency source means for generating a data clock signal, a carrier frequency signal and a shift register clock signal, the carrier signal having three voltage components consisting of a first carrier function voltage, a second carrier function voltage of the same frequency as the first carrier function voltage and in 180* phase relationship therewith, and a third component being zero volts, vector waveform generating means comprising three electrical conductors respectively supplied with the three voltage components of the carrier signal, a plurality of first resistor means having first ends connected selectively to the two electrical conductors supplied with the first and second carrier function voltages, second ends of said first resistor means connected to the third electrical conductor supplied with the third component of zero volts, each first resistor means provided with a tap point at which is developed a weighted sum of the selected voltage components of the carrier signal thereby providing a controlled phasing or vector rotation of the resultant carrier frequency voltage signal, a like plurality of second resistor means having first ends thereof adapted to be sequentially electrically connected to the tap points of associated said first resistor means and having second ends connected to a current summing means, digital control means for producing a train of contiguous equal duration pulses in response to a single data signal applied to a data signal input of said digital control means, the duration of each pulse determined by the frequency of the clock signal applied to a clock input of said digital control means, a like plurality of switch means operatively responsive to outputs of said digital control means for sequentially electrically connecting the first end of each of said second resistor means to the tap point of the associated first resistor means, the train of contiguous pulses determining the sequence and periods time periods of the nonoverlapping closed and resistor connecting states of said switch means thereby providing amplitude weighting of a like plurality of resultant sequentially generated phase controlled carrier current signal samples forming a desired signaling waveform in double side band modulated form at the output of the transmitter, and current summing means connected to the second ends of said second resistor means for summing the sequentially generated amplitude and phase controlled carrier current signal samples for transmission over a communication channel in response to the single data signal applied to the data signal input of said digital control means.

Claim 16

The data communication transmitter set forth in claim 12 wherein the resistance value of said first and second resistor means are selected to obtain equal average values of the carrier current signal samples of both positive and negative polarity sign to thereby obtain a suppressed carrier mode of transmission.

Claim 17

The data communication transmitter set forth in claim 1 wherein said current summing means comprises a current summing buss connected to the second ends of said second resistor means, and a current summing amplifier having an input connected to said current summing buss.

Claim 18

A data communication transmitter utilizing a vector waveform generator for simultaneously generating a desired signaling waveform and performing a desired modulation process for transmission over a communication channel in response to a data signal input and comprising frequency source means for generating a data clock signal, a carrier frequency signal and a shift register clock signal, the carrier frequency signal comprising a first voltage of square waveform, a second voltage in square waveform of the same frequency as the first square wave and in 90* phase lagging relationship therewith, a third voltage of square waveform of the same frequency as the first square wave and in 180* phase lagging relationship therewith, and a fourth voltage of square waveform of the same frequency as the first square wave and in 270* phase lagging relationship therewith, a vector waveform generator comprising first, second, third and fourth electrical conductors respectively supplied with the first, second, third and fourth square waveform carrier frequency voltages, a plurality of first resistors each having first ends thereof connected selectively to one of said first and third electrical conductors, a like plurality of second resistors each having first ends thereof connected selectively to one of said second and fourth electrical conductors, second ends of said first resistors respectively connected to second ends of associated said second resistors at which junctures are developed weighted sums of the selected square wave voltage components of the carrier frequency signal thereby providing a controlled phasing or vector rotation of the resultant carrier frequency voltage signal, a like plurality of third resistors having first ends thereof respectively adapted to be sequentially electrically connected to the junctures of associated said first and second resistors, a shift register for producing a train of contiguous pulses at the outputs thereof in response to a single data signal applied to a data signal input thereof, the duration of each pulse determined by the frequency of the clock signal applied to a clock input of said shift register, a like plurality of switch means operatively responsive to the pulse outputs of said shift register for sequentially electrically connecting the first ends of said third resistors to the junctures of the associated first and second resistors, the train of contiguous pulses developed at the outputs of said shift register determining the sequence and time periods of the closed states of said switch means thereby providing amplitude weighting of a like plurality of resultant sequentially generated phase controlled carrier current signal samples forming a desired signaling waveform in a single sideband modulated form, a current summing buss connected to second ends of said third resistors, and a current summing amplifier having an input connected to said current summing buss for summing the sequentially generated amplitude and phase controlled carrier current signal samples for transmission over a communication channel in response to the single data applied to the data signal input of said shift register.

Claim 19

A data communication transmitter utilizing a vector waveform generator for simultaneously generating a desired signaling waveform and performing a desired modulation process for transmission over a communication channel in response to a data signal input and comprising frequency source means for generating a data clock signal, a carrier frequency signal and a shift register clock signal, the carrier frequency signal comprising a first voltage of square waveform, a second voltage in square waveform of the same frequency as the first square wave and in 90* phase lagging relationship therewith, a third voltage of square waveform of the same frequency as the first square wave and in 180* phase lagging relationship therewith, and a fourth voltage of square waveform of the same frequency as the first square wave and in 270* phase lagging relationship therewith, a vector waveform generator comprising first, second, third and fourth electrical conductors respectively supplied with the first, second, third and fourth square waveform carrier frequency voltages, a plurality of first resistors each having first ends thereof connected selectively to one of said first and third electrical conductors, a like plurality of second resistors each having first ends thereof connected selectively to one of said second and fourth electrical conductors, second ends of said first resistors respectively connected to second ends of associated said second resistors at which junctures are developed weighted sums of the selected square wave voltage components of the carrier frequency signal thereby providing a controlled phasing or vector rotation of the resultant carrier frequency voltage signal, a like plurality of third resistors having first ends thereof respectively adapted to be sequentially electrically connected to the junctures of associated said first and second resistors, a shift register for producing a train of contiguous pulses at the outputs thereof in response to a single data signal applied to a data signal input thereof, the duration of each pulse determined by the frequency of the clock signal applied to a clock input of said shift register, a like plurality of switch means operatively responsive to the pulse outputs of said shift register for sequentially electrically connecting the first ends of said third resistors to the junctures of the associated first and second resistors, the train of contiguous pulses developed at the outputs of said shift register determining the sequence and time periods of the closed states of said switch means thereby providing amplitude weighting of a like plurality of resultant sequentially generated phase controlled carrier current signal samples forming a desired signaling waveform in a single sideband modulated form, a current summing buss connected to second ends of said third resistors, and a current summing amplifier having an input connected to said current summing buss for summing the sequentially generated amplitude and phase controlled carrier current signal samples for transmission over a communication channel in response to the single data applied to the data signal input of said shift register.

Claim 20

The data communication transmitter set forth in claim 15 wherein said frequency source means comprises an oscillator for generating a relatively high frequency signal, digital logic means for performing count-down functions to establish desired lower frequency values of the data clock, carrier frequency and shift register clock signals in square waveform.

Claim 21

The data communication transmitter set forth in claim 15 wherein said plurality of said first and second resistors are each of fixed resistance value selected in accordance with the desired signaling waveform.

Claim 22

The data communication transmitter set forth in claim 15 wherein said plurality of first and second resistors are each variable in resistance value to thereby obtain desired resistance values in accordance with the desired signaling waveform.

Claim 23

The data communication transmitter set forth in claim 15 wherein said plurality of switch means consists of a like plurality of switching transistors having gate electrodes thereof electrically connected to associated outputs of said shift register.

Claim 24

The data communication transmitter set forth in claim 19 wherein said shift register is comprised of a plurality of stages of number equal to the plurality of switching transistors whereby the gate electrodes of said transistors are associated respectively with a like plurality of outputs of said shift register, the clock input of said shift register supplied with the shift register cLock signal.

Claim 25

The data communication transmitter set forth in claim 19 wherein said shift register is comprised of a plurality of stages of number equal to the plurality of switching transistors divided by an integer which represents the ratio of the shift register to data clock frequencies, the clock input of said shift register supplied with the data clock signal, a plurality of logic AND gates of number equal to the plurality of said switching transistors and arranged in groups of number equal to the ratio of the shift register to data clock frequencies wherein each group thereof has a first input connected to a common associated shift register output, outputs of said plurality of AND gates connected respectively to gate electrodes of associated said switching transistors, and digital logic means having an input supplied with the shift register clock signal for cycling at the shift register clock frequency a single output pulse at a plurality of outputs thereof of number equal to the ratio of shift register to data clock frequencies, outputs of said cycling logic means connected respectively to second inputs of the AND gates in each group thereof whereby the plurality of AND gates sequentially electrically connect the junctures of th first and second resistors with the associated third resistors to form the resultant sequentially generated phase controlled carrier current signal samples.

Claim 26

The data communication transmitter set forth in claim 1 and further comprising low-pass filter means connected to the output of said current summing means for smoothing the modulated form of the desired signaling waveform which is a stepped approximation to the desired modulated signal to thereby band-limit the modulated output waveform to the channel bandwidth.

Claim 27

The data communication transmitter set forth in claim 22 and further comprising a power amplifier connected to an output of said low-pass filter means, output of said amplifier transformer coupled to the communication channel for matching the communication channel termination impedance.

Claim 28

The data communication transmitter set forth in claim 1 and further comprising a plurality of power amplifiers having inputs respectively connected to the carrier signal outputs of said frequency source means, and outputs respectively connected to said electrical conductor means for supplying the required electric current thereto, said amplifiers being switching devices in the case of the carrier frequency signal components being of square waveform thereby providing the transmitter with capability for being manufactured by integrated circuit technology.