US3793513A
Expired / Lapsed
US
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Circuits and methods for processing delta-modulated signals
Assignee: NEC Corp
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Filing: 1972-05-15
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Granted: 1974-02-19
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Expires: 1992-05-15
Abstract
Abstract A delta-modulated signal processing circuit includes one or more first multipliers for multiplying one or more delta-modulated input signals by preselected constants, thus producing a first code signal corresponding to each first multiplier. A second multiplier is provided for multiplying a delta-modulated output signal by a second constant having a sign opposite to that of the first constants to provide a second code signal. A digital adder takes the algebraic sum of the first and second code signals. The output of the digital adder is applied to an integrator to produce an output signal including sign-indicating bits. Also included in the circuit is a sign-bit extractor for extracting the sign-indicating bits from the output of the integrator. This provides the delta-modulated signal supplied to the second multiplier. Modifications of this circuit for various uses are disclosed.
Inventors
- 👤 H Kaneko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:50
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/04; H03H17/0411
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
105 words
A delta-modulated signal processing circuit comprising: first multiplier means for multiplying a delta-modulated input signal by a first constant to provide a first code signal, second multiplier means for multiplying a delta-modulated output signal by a second constant to provide a second code signal, digital adder means for taking an algebraic sum of said first and second code signals, digital integrator means for integrating the output of said digital adder means to produce a signal including sign indicating bits and sign bit extracting means for extracting the sign indicating bits from the output signals of said digital integrator means thereby providing said delta-modulated output signal.
Claim 2
Dependent Claim
105 words
A delta-modulated signal processing circuit comprising: first multiplier means for multiplying a delta-modulated input signal by a first constant to provide a first code signal, second multiplier means for multiplying a delta-modulated output signal by a second constant to provide a second code signal, digital adder means for taking an algebraic sum of said first and second code signals, digital integrator means for integrating the output of said digital adder means to produce a signal including sign indicating bits and sign bit extracting means for extracting the sign indicating bits from the output signals of said digital integrator means thereby providing said delta-modulated output signal.
Claim 3
Dependent Claim
22 words
A delta-modulated signal processing circuit according to claim 1, wherein at least one of said constants has an absolute value of one.
Claim 4
Dependent Claim
59 words
A delta-modulated signal processing circuit according to claim 1, further comprising a delay means for causing the said second code signal to be supplied to said digital adder means at a time later than the time at which the portion of said first code signal from which said second code signal is derived arrives at the digital adder means.
Claim 5
Dependent Claim
80 words
A delta-modulated signal processing circuit comprising digital adder means for taking an algebraic sum of at least two delta-modulated input signals and a coded output signal, digital integrator means for integrating the output of the digital adder means to produce a signal including sign-indicating bits, and sign-bit extractor means for extracting the sign-indicating bits from the output signals of said digital integrator means, the output of said extractor means being supplied to said adder means as said coded output signal.
Claim 6
Dependent Claim
80 words
A delta-modulated signal processing circuit comprising digital adder means for taking an algebraic sum of at least two delta-modulated input signals and a coded output signal, digital integrator means for integrating the output of the digital adder means to produce a signal including sign-indicating bits, and sign-bit extractor means for extracting the sign-indicating bits from the output signals of said digital integrator means, the output of said extractor means being supplied to said adder means as said coded output signal.
Claim 7
Independent Claim
87 words
A method of processing a delta-modulated signal comprising: multiplying a delta-modulated input signal by a first constant to provide a first code signal; algebraically adding the first code signal to a previously derived second code signal; integrating the algebraically added signals to produce a signal including sign-indicating bits; extracting the sign-indicating bit from the signal produced by integration, thereby providing a delta-modulated output signal; and multiplying the delta-modulated output signal by a second constant to provide said second code signal for addition to the first code signal.
Claim 8
Independent Claim
87 words
A method of processing a delta-modulated signal comprising: multiplying a delta-modulated input signal by a first constant to provide a first code signal; algebraically adding the first code signal to a previously derived second code signal; integrating the algebraically added signals to produce a signal including sign-indicating bits; extracting the sign-indicating bit from the signal produced by integration, thereby providing a delta-modulated output signal; and multiplying the delta-modulated output signal by a second constant to provide said second code signal for addition to the first code signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-18 | 1977-08-20 | 1978-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-18 | 1981-08-20 | 1982-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-18 | 1985-08-20 | 1986-02-19 | $7700.00 | Window Closed / Lapsed |