US3792441A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Micro-program having an overlay micro-instruction
Assignee: Unisys Corp
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Filing: 1972-03-08
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Granted: 1974-02-12
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Expires: 1992-03-08
Abstract
Abstract There is described a micro-programmed data processor having, in addition to the main memory, a memory for currently used strings of micro-operators in which any portion of the latter memory can be overlayed from main memory by a unique micro-instruction that is handled as one more micro step in whatever micro-string is being executed. Once the overlay is complete, the next microoperation in sequence is executed. This micro-operator may be from the previously stored micro-operator string or from the overlayed instructions, depending upon where the overlay is positioned in the memory.
Inventors
- 👤 C Wymore
- 👤 Cain P Le
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:23
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/322; G06F9/328; G06F9/22; G06F9/24
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
197 words
In a micro-programmed processor, apparatus comprising: an addressable main memory storing micro-instructions in fields, the micro-instructions in a field being stored in sequential address locations, an addressable auxiliary memory storing microinstructions, a micro-instruction register, means including an address register for transferring micro-instructions in sequence from the auxiliary memory to the micro-instruction register, means setting the address register to the address of the next micro-instruction with each transfer of a micro-instruction to the micro-instruction register, a temporary storage unit, control means responsive to a predetermined micro-instruction in the micro-instruction register, the control means including means for transferring the address pointing to the location in the auxiliary memory of the next micro-instruction from said address register to the temporary storage unit, means for setting the address register to any predetermined address, and means for transferring micro-instructions sequentially from a field in the main memory to sequential address locations in the auxiliary memory, the sequential address locations in the auxiliary memory starting at said predetermined address in the address register, means sensing when the last micro-instruction in the field has been transferred to the auxiliary memory for resetting the address register to the address stored in the temporary storage unit.
Claim 2
Dependent Claim
197 words
In a micro-programmed processor, apparatus comprising: an addressable main memory storing micro-instructions in fields, the micro-instructions in a field being stored in sequential address locations, an addressable auxiliary memory storing microinstructions, a micro-instruction register, means including an address register for transferring micro-instructions in sequence from the auxiliary memory to the micro-instruction register, means setting the address register to the address of the next micro-instruction with each transfer of a micro-instruction to the micro-instruction register, a temporary storage unit, control means responsive to a predetermined micro-instruction in the micro-instruction register, the control means including means for transferring the address pointing to the location in the auxiliary memory of the next micro-instruction from said address register to the temporary storage unit, means for setting the address register to any predetermined address, and means for transferring micro-instructions sequentially from a field in the main memory to sequential address locations in the auxiliary memory, the sequential address locations in the auxiliary memory starting at said predetermined address in the address register, means sensing when the last micro-instruction in the field has been transferred to the auxiliary memory for resetting the address register to the address stored in the temporary storage unit.
Claim 3
Dependent Claim
80 words
Apparatus of claim 1 wherein said means sensing when the last micro-inStruction is transferred includes a field length register storing the length of said field of micro-instructions to be transferred from the main memory to the auxiliary memory, means decrementing the contents of the field length register as each micro-instruction is transferred to the auxiliary memory, and means responsive to the field length register when the contents are decremented to zero for signaling that the complete field has been transferred.
Claim 4
Dependent Claim
61 words
Apparatus of claim 2 further including means sensing when the maximum capacity of the auxiliary memory is reached in transferring the micro-instructions from main memory into the auxiliary memory, and means sensing when the maximum capacity of the auxiliary memory is reached during the transfer of micro-instructions into the auxiliary memory for resetting the address register from the temporary storage unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-11 | 1977-08-13 | 1978-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-11 | 1981-08-13 | 1982-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-11 | 1985-08-13 | 1986-02-12 | $7700.00 | Window Closed / Lapsed |