Patent US3792436A successfully refreshed from Google Patents.
US3792436A
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Deskewing buffer arrangement which includes means for detecting and correcting channel errors
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1973-01-04
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Granted: 1974-02-12
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Expires: 1993-01-04
Abstract
Abstract A deskewing buffer system includes a plurality of storage registers each of which include a plurality of storage devices. Pairs of the storage devices provide storage for a single information channel. The devices of each channel further includes circuits for detecting when no information has been stored by an input pair of storage devices of a channel within a bit interval which signals a dropped bit within the channel. The detection circuits are then operative to switch both input storage devices of the channel to the same predetermined state. Thereafter, checking circuits coupled to a last register of the buffer system are operative to check the deskewed contents of the register and generate a signal indicating whether the channel dropped a binary ONE or binary ZERO bit. The signal is then used to transfer selectively the state of one of the pairs of storage devices of the channel to an output register.
Inventors
- 👤 J Klashka
- 👤 Voy D De
- 👤 G Barlow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:13
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419; G11B20/18; G11B20/20
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
471 words
Apparatus for detecting and correcting for the occurrence of dropped pulses from information pulses of bytes of information read during bit intervals from any one of a plurality of information channels of a storage medium by a corresponding number of sense circuits, the sense circuit of each channel being operative to provide pulses to first and second output lines, said pulses applied to said first line representing a binary ONE and said pulses applied to said second line representing a binary ZERO, each sense circuit providing normally at least one pulse during each bit interval and each byte of information corresponding to a group of bit signals simultaneously recorded on said medium in each of said information channels, said apparatus comprising: a plurality of deskewing buffer registers, each of said registers including first and second bistable storage means coupled to be individually associated with one of said sense circuits; said first and second bistable storage means for a first one of said buffer registers of each channel being coupled to receive pulses applied to said first and second lines respectively; means for applying first and second sets of synchronous clocking signals defining each bit interval to said first and second bistable storage means of said first one of said buffer registers of each channel, said first and second bistable storage means being conditioned by said first set of clocking signals to switch from a binary ZERO to a binary ONE gate in response to pulses applied from said first and second lines respectively; logic sensing means individually coupled to said first and second bistable means of said first register of each channel, said sensing means being conditioned by said first and second bistable means when in said binary ZERO states to switch both said first and second bistable means to a binary ONE state in response to one of said clocking signals of said second set to signal an occurrence of a dropped pulse within said channel; checking means coupled to a last one of said buffer registerS, said checking means being operative to perform a vertical check upon the contents of each of said first bistable means of each channel corresponding to an assembled byte of information, said checking means being operative in accordance with the results of said vertical check to generate an error correction signal signalling that information stored in said first bistable means of the channel signalling said occurrence of said dropped pulse requires correction; and, logic gating means coupled to said first bistable means of said last one of said buffer registers of each channel, the logic gating means of said channel signalling said occurrence of said dropped pulse being conditioned by said signal to transfer selectively the contents of said first bistable means correcting a corresponding one of the bit position of said assembled byte.
Claim 2
Dependent Claim
471 words
Apparatus for detecting and correcting for the occurrence of dropped pulses from information pulses of bytes of information read during bit intervals from any one of a plurality of information channels of a storage medium by a corresponding number of sense circuits, the sense circuit of each channel being operative to provide pulses to first and second output lines, said pulses applied to said first line representing a binary ONE and said pulses applied to said second line representing a binary ZERO, each sense circuit providing normally at least one pulse during each bit interval and each byte of information corresponding to a group of bit signals simultaneously recorded on said medium in each of said information channels, said apparatus comprising: a plurality of deskewing buffer registers, each of said registers including first and second bistable storage means coupled to be individually associated with one of said sense circuits; said first and second bistable storage means for a first one of said buffer registers of each channel being coupled to receive pulses applied to said first and second lines respectively; means for applying first and second sets of synchronous clocking signals defining each bit interval to said first and second bistable storage means of said first one of said buffer registers of each channel, said first and second bistable storage means being conditioned by said first set of clocking signals to switch from a binary ZERO to a binary ONE gate in response to pulses applied from said first and second lines respectively; logic sensing means individually coupled to said first and second bistable means of said first register of each channel, said sensing means being conditioned by said first and second bistable means when in said binary ZERO states to switch both said first and second bistable means to a binary ONE state in response to one of said clocking signals of said second set to signal an occurrence of a dropped pulse within said channel; checking means coupled to a last one of said buffer registerS, said checking means being operative to perform a vertical check upon the contents of each of said first bistable means of each channel corresponding to an assembled byte of information, said checking means being operative in accordance with the results of said vertical check to generate an error correction signal signalling that information stored in said first bistable means of the channel signalling said occurrence of said dropped pulse requires correction; and, logic gating means coupled to said first bistable means of said last one of said buffer registers of each channel, the logic gating means of said channel signalling said occurrence of said dropped pulse being conditioned by said signal to transfer selectively the contents of said first bistable means correcting a corresponding one of the bit position of said assembled byte.
Claim 3
Dependent Claim
188 words
The apparatus of claim 1 further including: gating means coupled to said first and second bistable storage means of said last one of said registers of each channel, said gating means being operative to generate a signal indicating said occurrence of a dropped pulse within said channel when said first and second bistable storage means are both in a binary ONE state; and, a multistage data register for receiving said assembled byte signals, each stage of said data register including a pair of input gating means, one of said pair being coupled individually to one of said first bistable means of said last one of said registers of a channel and to said checking means, the other one of said pair being coupled to said first bistable means and to the sensing means of said channel, said other one of said gating means being conditioned by said signal from said gating means to inhibit the transfer of the contents of said first bistable means and said other one of said gating means being conditioned by said error signal to transfer selectively said contents of said first bistable means.
Claim 4
Dependent Claim
18 words
The apparatus of claim 2 wherein each of said pair of input gating means includes an AND gate.
Claim 5
Dependent Claim
78 words
The apparatus of claim 1 further including first and second synchronous bistable storage elements coupled to receive first and second sets of asynchronous clocking signals respectively, each of said first and second bistable elements including means for receiving synchronous clocking signals, said first and second bistable elements being conditioned by said synchronous clocking signals to switch from a first to a second state in response to said sets of asynchronous clocking signals to produce said synchronous clocking signals.
Claim 6
Dependent Claim
69 words
The apparatus of claim 1 wherein said logic sensing means includes bistate switching means, said bistate switching means being operative in response to said first set of synchronous clocking signals to switch from a first to a second state, and said bistate switching means being operative in response to one of said first and second bistable means being switched to a binary ONE to switch to a binary ZERO.
Claim 7
Dependent Claim
77 words
The apparatus of claim 1 wherein said checking means includes: parity generation means, said parity generation means being operative to generate odd parity check signal for said assembled byte; and, gating means coupled to said parity generation means, said gating means being conditioned by said check signal to force said error correction signal to a binary ONE and a binary ZERO respectively when said channel dropped a pulse representative of a binary ONE and a binary ZERO.
Claim 8
Dependent Claim
172 words
The apparatus of claim 1 wherein said first and second bistable storage means of said first one of said registers each include; first and second gating means, said first gating means of said first bistable storage means being coupled to said first line and coupled to receive said first set of clocking signals, said first gating means of said second bistable storage means being coupled to said second line and coupled to receive said first set of clocking signals, said seocnd gating means of said first and second bistAble means each being coupled to receive said second set of clocking signals and coupled to said logic sensing means, and first gating means of said first and second bistable means being operative to switch a corresponding one of said bistable means to a binary ONE state in response to said pulses and said second gating means of said first and second bistable means being conditioned by said logic sensing means to switch said first and second bistable means to said binary ONE state.
Claim 9
Dependent Claim
105 words
The apparatus of claim 1 wherein said first and second bistable storage means of each of said registers are coupled to receive clocking signals and wherein said first one of said registers includes gating means connected between any two registers for switching to a binary ONE state said bistable storage means of a succeeding register in response to the bistable storage means of a preceding register being switched to a binary ONE and said bistable storage means of said succeeding register being a binary ZERO upon the occurrence of one of said clocking signals thereby enabling synchronous transfers of information between each of said registers.
Claim 10
Dependent Claim
61 words
The apparatus of claim 1 further including multiple error sensing means coupled to said first and second bistable means of said last one of said registers of each channel, said multiple error sensing means being operative to generate an output signal upon sensing that more than one pair of said first and second bistable means is in a binary ONE state.
Claim 11
Dependent Claim
452 words
In a multichannel record recovery system apparatus for detecting and correcting for the occurrence of dropped pulses from information pulses of bytes of information read during bit intervals by a plurality of sense circuits from any one of the information channels of a magnetic medium subject to skew a predetermined maximum number of bit positions, the sense circuit of each channel being operative to provide pulses to first and second output lines respectively representative of binary ONE and binary ZERO data and at least one pulse during each bit interval, said system having a predetermined number of deskew registers for accommodating said skew, each of said registers including first and second bistable means individually associated with each of said sense circuits for receiving pulses from said first and second output lines, said apparatus comprising: means for applying first and second sets of synchronous sets of clocking signals defining each bit interval to said first and second bistable means of a first one of said registers of each channel, each of said first and second bistable means being coupled to said first and second output lines respectively and conditioned by said clocking signals to switch from a first state to second and third states in response to pulses applied to said lines; sensing means individually coupled to said first and second bistable means of said first one of said registers of each channel, said sensing means being conditioned by said first and second bistable means when in said first state to switch both of said first and second bistable means to a fourth state at the end of a bit interval in response to one of said clocking signals of said second set signalling an occurrence of a dropped pulse within said channel; checking means coupled to predetermined ones of said first and second bistable means of a last one of said registers of each channel, said checking means being operative to perform a vertical check upon the bits of a byte assembled in said last one of said registers, said checking means being operative in accordance with the results of said check to generate one level of a bilevel output signal indicating that the channel signalling said occurrence, dropped a pulse representative of a binary ONE or a binary ZERO; and, logic gating means coupled to receive signals from said first bistable means of said last one of said registers of each channel, said logic gating means of said channel signalling said occurrence beIng conditioned by said one level of said bilevel output signal to transfer selectively the contents of said first bistable means so as to correct the information of a corresponding one of the bit positions of said assembled byte.
Claim 12
Dependent Claim
452 words
In a multichannel record recovery system apparatus for detecting and correcting for the occurrence of dropped pulses from information pulses of bytes of information read during bit intervals by a plurality of sense circuits from any one of the information channels of a magnetic medium subject to skew a predetermined maximum number of bit positions, the sense circuit of each channel being operative to provide pulses to first and second output lines respectively representative of binary ONE and binary ZERO data and at least one pulse during each bit interval, said system having a predetermined number of deskew registers for accommodating said skew, each of said registers including first and second bistable means individually associated with each of said sense circuits for receiving pulses from said first and second output lines, said apparatus comprising: means for applying first and second sets of synchronous sets of clocking signals defining each bit interval to said first and second bistable means of a first one of said registers of each channel, each of said first and second bistable means being coupled to said first and second output lines respectively and conditioned by said clocking signals to switch from a first state to second and third states in response to pulses applied to said lines; sensing means individually coupled to said first and second bistable means of said first one of said registers of each channel, said sensing means being conditioned by said first and second bistable means when in said first state to switch both of said first and second bistable means to a fourth state at the end of a bit interval in response to one of said clocking signals of said second set signalling an occurrence of a dropped pulse within said channel; checking means coupled to predetermined ones of said first and second bistable means of a last one of said registers of each channel, said checking means being operative to perform a vertical check upon the bits of a byte assembled in said last one of said registers, said checking means being operative in accordance with the results of said check to generate one level of a bilevel output signal indicating that the channel signalling said occurrence, dropped a pulse representative of a binary ONE or a binary ZERO; and, logic gating means coupled to receive signals from said first bistable means of said last one of said registers of each channel, said logic gating means of said channel signalling said occurrence beIng conditioned by said one level of said bilevel output signal to transfer selectively the contents of said first bistable means so as to correct the information of a corresponding one of the bit positions of said assembled byte.
Claim 13
Dependent Claim
192 words
The system of claim 10 wherein said apparatus further includes: gating means coupled to said first and second bistable storage means of said last one of said registers of each channel, said gating means being conditioned to generate an error signal indicating said occurrence of a dropped pulse within said channel when said first and second bistable storage means have been switched to said fourth state; and, a multistage data register for receiving said assembled byte signals, each state of said data register including a pair of input gating means, one of said pair being coupled individually to one of said first bistable means of said last one of said registers of a channel and to said checking means, the other one of said pair being coupled to said first bistable means and to the sensing means of said channel, said other one of said gating means being conditioned by said signal from said gating means to inhibit the transfer of the contents of said first bistable means and said other one of said gating means being conditioned by said error signal to transfer selectively said contents of said first bistable means.
Claim 14
Dependent Claim
18 words
The system of claim 11 wherein each of said pair of input gating means includes an AND gate.
Claim 15
Dependent Claim
81 words
The system of claim 10 wherein said apparatus further includes first and second synchronous bistable storage elements coupled to receive first and second sets of asynchronous clocking signals respectively, each of said first and second bistable elements including means for receiving synchronous clocking signals, said first and second bistable elements being conditioned by said synchronous clocking signals to switch from a first to a second state in response to said sets of asynchronous clocking signals to produce said synchronous clocking signals.
Claim 16
Dependent Claim
69 words
The system of claim 10 wherein said logic sensing means includes bistate switching means, said bistate switching means being operative in response to said first set of synchronous clocking signals to switch from a first to a second state and said bistable switching means being operative in response to one of said first and second bistable means being switched to a binary ONE to switch to a binary ZERO.
Claim 17
Dependent Claim
77 words
The system of claim 10 wherein said checking means includes: parity generation means, said parity generation means being operative to generate odd parity check signal for said assembled byte; and, gating means coupled to said parity generation means, said gating means being conditioned by said check signal to force said error correction signal to a binary ONE and a binary ZERO respectively when said channel dropped a pulse representative of a binary ONE and a binary ZERO.
Claim 18
Dependent Claim
114 words
The system of claim 15 wherein said apparatus further includes: means for generating a signal indicating when said last one of said registers stores an assembled byte, said means being coupled to each of said first and second bistable means of said last one of said registers of each channel, said means being operative to generate said signal upon at least one of said first and second bistable means of each channel has switched to a binary ONE state; and, gating means coupled to said last mentioned means and to said parity generation means, said gating means being operative in response to said signal and said check signal to generate said error correction signal.
Claim 19
Dependent Claim
38 words
The system of claim 10 wherein said first and second bistable means when switched to said first state, said second state, said third state and said fourth state respectively store information codes of 00, 10, 01 and 11.
Claim 20
Dependent Claim
319 words
A data recovery system for reliably processing information recorded within a plurality of channels as a series of transitions occurring within a correspoNding number of bit intervals, at least one transition occurring within each bit interval, said system comprising: a plurality of deskewing buffer register means for accommodating a skew of a predetermined maximum number of bit positions, each of said register means including a pair of bistable storage means, each pair of a first one of said register means being individually associated with one of said channels for receiving pulses representative of binary ONE and binary ZERO data defined by said transitions; means for applying first and second sets of clocking signals defining said bit intervals to first and second bistable storage means respectively of each pair of said first one of said register means for switching said pair from a first state to second and third states in response to pulses received during said intervals; logic sensing means individually coupled to each pair of bistable storage means of said first one of said register means, said sensing means being conditioned by said each pair when in said first state at the end of a bit interval to switch said pair to a fourth state in response to one of said clocking signals of said second set signalling to the remaining system of an occurrence of a dropped pulse within said channel; and, checking means coupled to predetermined ones of each pair of bistable storage means of a last one of said register means, said checking means being operative to perform a vertical check upon the bits of a byte assembled in said last one of said register means, said checking means being operative in accordance with the results to generate an output signal indicating that the information stored in said pair of bistable storage means of a channel signalling said occurrence of said dropped pulse requires correction.
Claim 21
Dependent Claim
319 words
A data recovery system for reliably processing information recorded within a plurality of channels as a series of transitions occurring within a correspoNding number of bit intervals, at least one transition occurring within each bit interval, said system comprising: a plurality of deskewing buffer register means for accommodating a skew of a predetermined maximum number of bit positions, each of said register means including a pair of bistable storage means, each pair of a first one of said register means being individually associated with one of said channels for receiving pulses representative of binary ONE and binary ZERO data defined by said transitions; means for applying first and second sets of clocking signals defining said bit intervals to first and second bistable storage means respectively of each pair of said first one of said register means for switching said pair from a first state to second and third states in response to pulses received during said intervals; logic sensing means individually coupled to each pair of bistable storage means of said first one of said register means, said sensing means being conditioned by said each pair when in said first state at the end of a bit interval to switch said pair to a fourth state in response to one of said clocking signals of said second set signalling to the remaining system of an occurrence of a dropped pulse within said channel; and, checking means coupled to predetermined ones of each pair of bistable storage means of a last one of said register means, said checking means being operative to perform a vertical check upon the bits of a byte assembled in said last one of said register means, said checking means being operative in accordance with the results to generate an output signal indicating that the information stored in said pair of bistable storage means of a channel signalling said occurrence of said dropped pulse requires correction.
Claim 22
Dependent Claim
81 words
The system of claim 18 further including: register means having a plurality of stages for receiving said assembled byte signals; and, logic gating means coupled to receive signals from first bistable means of each pair of said last one of said register means, said logic means of each said channel signalling said occurrence, being conditioned by said output signal to inhibit the transfer of information stored in said first bistable means to a corresponding one of said stages correcting said information.
Claim 23
Dependent Claim
41 words
The system of claim 18 wherein said first and second bistable means of said pair when switched to said first state, said second state, said third state and said fourth state respectively store information codes of 00, 10, 01 and 11.
Claim 24
Dependent Claim
188 words
The system of claim 18 further including: gating means coupled to said first and second bistable storage means of said last one of said registers of each channel, said gating means being operative to generate a signal indicating said occurrence of a dropped pulse within said channel when said first and second bistable storage means are both in a binary ONE state; and, a multistage data register for receiving said assembled byte signals, each stage of said data register including a pair of input gating means, one of said pair being coupled individually to one of said first bistable means of said last one of said registers of a channel and to said checking means, the other one of said pair being coupled to said first bistable means and to the sensing means of said channel, said other one of said gating means being conditioned by said signal from said gating means to inhibit the transfer of the contents of said first bistable means and said other one of said gating means being conditioned by said error signal to transfer selectively said contents of said first bistable means.
Claim 25
Dependent Claim
78 words
The system of claim 18 further including first and second synchronous bistable storage elements coupled to receive first and second sets of asynchronous clocking signals respectively, each of said first and second bistable elements including means for receiving synchronous clocking signals, said first and second bistable elements being conditioned by said synchronous clocking signals to switch from a first to a second state in response to said sets of asynchronous clocking signals to produce said synchronous clocking signals.
References Cited (Backward Citations)
US3193812A
Cited
USPTO Annuity & Maintenance Windows
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| 7.5 Years (Year 8) | 1981-02-11 | 1981-08-13 | 1982-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-11 | 1985-08-13 | 1986-02-12 | $7700.00 | Window Closed / Lapsed |