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US3792355A
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Orthogonal transformation circuit using hadamard matrices
Assignee: Hitachi Ltd
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Filing: 1971-12-10
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Granted: 1974-02-12
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Expires: 1991-12-10
Abstract
Abstract An orthogonal transformation circuit in which unit transformation circuits are connected in cascade in accordance with a desired order of transformation. Each unit transformation circuit comprises a first delay circuit which delays discrete signals by a fixed time, an arithmetic circuit which provides the sum and difference between input and output signals of the delay circuit, a second delay circuit which delays the difference signal of the arithmetic circuit by the same delay time as that of said first delay circuit, and a gate circuit which provides output signals such that the sum signal from the arithmetic circuit and the difference signal from the second delay circuit are alternated at a fixed time interval.
Inventors
- 👤 M Miyata
- 👤 T Fukinuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:54
CPC Classifications
H; H04; H04J; H04J13/00; H04J13/0007; H04J13/004; H04J13/0048; H04J13/10; H04J13/12; H04L; H04L23/00; H04L23/02
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
135 words
An orthogonal transformation circuit including at least one unit transformation circuit for transforming discrete signals occurring at a predetermined period T, each unit transformation circuit comprising an input terminal for receiving the discrete signals to be transformed which occur at the period T, first delay means connected to said input terminal and having a delay period of 2k . T where k 0, 1, 2, 3 . . . n-1, arithmetic circuit means connected to the output of said first delay means and to said input terminal for alternately providing output signals at the period 2k . T of said first delay means that are a sum signal and a difference signal from said first delay means and a signal from said input terminal, and an output terminal being connected to said arithmetic circuit means.
Claim 2
Dependent Claim
135 words
An orthogonal transformation circuit including at least one unit transformation circuit for transforming discrete signals occurring at a predetermined period T, each unit transformation circuit comprising an input terminal for receiving the discrete signals to be transformed which occur at the period T, first delay means connected to said input terminal and having a delay period of 2k . T where k 0, 1, 2, 3 . . . n-1, arithmetic circuit means connected to the output of said first delay means and to said input terminal for alternately providing output signals at the period 2k . T of said first delay means that are a sum signal and a difference signal from said first delay means and a signal from said input terminal, and an output terminal being connected to said arithmetic circuit means.
Claim 3
Dependent Claim
17 words
An orthogonal transformation circuit according to claim 1, wherein said arithmetic circuit means is a digital circuit.
Claim 4
Dependent Claim
121 words
An orthogonal transformation circuit according to claim 1, wherein said arithmetic circuit means comprises adder means for providing an output signal which is the sum of the input and output of said first delay means, subtractor means for providing an output signal which is the difference of said input and output of said first delay means, second delay means connected to the output of said subtractor means and having the same delay period as said first delay means, and gating means for alternatively providing an output of said adder means and an output of said second delay means to said output terminal at a switching period which is the same as the delay period of said first and second delay means.
Claim 5
Dependent Claim
126 words
An orthogonal transformation circuit according to claim 1, wherein said arithmetic circuit means comprises an adder means for providing an output signal of the sum of the input and output signals which is said first delay means, second delay means having the same delay period as said first delay means, said second delay means being connected In series with said first delay means, subtractor means for providing an output signal which is the difference of input and output signals of said second delay means, and gating meanS for alternatively providing an output of said adder means and an output of said subtractor means to said output terminal at a switching period which is the same as the delay period of said first and second delay means.
Claim 6
Dependent Claim
153 words
An orthogonal transformation circuit according to claim 1, wherein said arithmetic circuit means comprises second delay means connected in series with said first delay means and having a delay period the same as said first delay means, negative logic means connected to an input of said second delay means for providing a negative output signal of the input signal applied thereto, first gating means alternately providing an output signal of the input of said first delay means and the output of the negative logic means, second gating means alternatively providing an output signal which is an input and an output of said second delay means, gate-driving signal circuit means for switching said respective gating means at the same time period as said delay period of said delay means, and adder means for providing an output signal of the sum of the outputs of said first and second gating means to said output terminal.
Claim 7
Dependent Claim
17 words
An orthogonal transformation circuit according to claim 1, wherein said unit transformation circuit is an integrated circuit.
Claim 8
Dependent Claim
42 words
An orthogonal transformation circuit according to claim 1 including n plurality of said unit transformation circuits connected in cascade where n is an integer, the delay and switching period 2k . T being different for each of said cascaded unit transformation circuits.
Claim 9
Dependent Claim
17 words
An orthogonal transformation circuit according to claim 7, wherein said arithmetic circuit means is a digital circuit.
Claim 10
Dependent Claim
121 words
An orthogonal transformation circuit according to claim 7, wherein said arithmetic circuit means comprises adder means for providing an output signal which is the sum of the input and output of said first delay means, subtractor means for providing an output signal which is the difference of said input and output of said first delay means, second delay means connected to the output of said subtractor means and having the same delay period as said first delay means, and gating means for alternately providing an output of said adder means and an output of said second delay means to said output terminal at a switching period which is the same as the delay period of said first and second delay means.
Claim 11
Dependent Claim
124 words
An orthogonal transformation circuit according to claim 7, wherein said arithmetic circuit means comprises an adder means for providing an output signal of the sum of the input and output signals of said first delay means, second delay means having the same delay period as said first delay means, said second delay means being connected in series with said first delay means, subtractor means for providing an output signal which is difference of input and output signals of said second delay means, and gating means for alternately providing an output of said adder means and an output of said subtractor means to said output terminal at a switching period which is the same as the delay period of said first and second delay means.
Claim 12
Dependent Claim
153 words
An orthogonal transformation circuit according to claim 7, wherein said arithmetic circuit means comprises second delay means connected in series with said first delay means and having a delay period the same as said first delay means, negative logic means connected to an input of said second delay means for providing a negative output signal of the input signal aPplied thereto, first gating means alternatively providing an output signal which is the input of said first delay means and the output of the negative logic means, second gating means alternately providing an output signal of an input and an output of said second delay means, gate-driving signal circuit means for switching said respEctive gating means at the same time period as said delay period of said delay means, and adder means for providing an output signal of the sum of the outputs of said first and second gating means to said output terminal.
Claim 13
Dependent Claim
149 words
A communication system having a transmitter station and a receiver station, each station having an orthogonal transformation circuit including at least one unit transformation circuit for transforming discrete signals occurring at a predetermined period T, each unit transformation circuit comprising an input terminal for receiving the discrete signals to be transformed which occur at the period T, first delay means connected to said input terminal and having a delay period of 2k . T where k 0, 1, 2, 3 . . . n-1, arithmetic circuit means connected to the output of said first delay means and to said input terminal for alternately providing output signals at the period 2k . T of said first delay means that are a sum signal and a difference signal from said first delay means and a signal from said input terminal, and an output terminal being connected to said arithmetic circuit means.
Claim 14
Dependent Claim
149 words
A communication system having a transmitter station and a receiver station, each station having an orthogonal transformation circuit including at least one unit transformation circuit for transforming discrete signals occurring at a predetermined period T, each unit transformation circuit comprising an input terminal for receiving the discrete signals to be transformed which occur at the period T, first delay means connected to said input terminal and having a delay period of 2k . T where k 0, 1, 2, 3 . . . n-1, arithmetic circuit means connected to the output of said first delay means and to said input terminal for alternately providing output signals at the period 2k . T of said first delay means that are a sum signal and a difference signal from said first delay means and a signal from said input terminal, and an output terminal being connected to said arithmetic circuit means.
Claim 15
Dependent Claim
78 words
A communication system according to claim 12, wherein said orthogonal transformation circuit includes n plurality of said unit transformation circuits connected in cascade where n is an integer, the delay and switching period 2k . T being different for each of said cascaded unit transformation circuits, said cascaded unit transformation circuits at said transmitter station being cascaded in a predetermined arrangement and said cascaded unit transformation circuits at said receiver station being cascaded inversely to said predetermined arrangement.
Claim 16
Dependent Claim
119 words
A communication system according to claim 12, wherein said arithmetic circuit means comprises adder means for providing an output signal which is the sum of the input and output of said first delay means, subtractor means for providing an output signal of the difference of said input and output of said first delay means, second delay means connected to the output of said subtractor means and having the same delay period as said first delay means, and gating means for alternately providing an output of said adder means and an output of said second delay means to said output terminal at a switching period which is the same as the delay period of said first and second delay means.
Claim 17
Dependent Claim
123 words
A communication system according to claim 12, wherein said arithmetic circuit means comprises an adder means for providing an output signal of the sum of the input and output signals of said first delay means, second delay means having the same delay period as said first delay means, said second delay means being connected in series with said first delay means, subtractor means for providing an output signal of the difference of input and output signals of said second delay means, and gating means for alternately providing an output of said adder means and an output of said subtractor means to said output terminal at a switching period which is the same as the delay period of said first and second delay means.
Claim 18
Dependent Claim
151 words
A communication system according to claim 12, wherein said arithmetic circuit means comprises second delay means connected in series with said first delay means and having a delay period the same as said first delay means, negative logic means connected to an input of said second delay means for providing a negative output signal of the input signal applied thereto, first gating means alternatively providing an output signal of the input of said first delay means and the output of the negative logic means, second gating means alternately providing an output signal of an input and an output of said second delay means, gate-driving signal circuit means for switching said respective gating means at the same time period as said delay period of said delay means, and adder means for providing an output signal of the sum of the outputs of said first and seconD gating means to said output terminal.
References Cited (Backward Citations)
US3089921A
Cited
US3611142A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-11 | 1977-08-13 | 1978-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-11 | 1981-08-13 | 1982-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-11 | 1985-08-13 | 1986-02-12 | $7700.00 | Window Closed / Lapsed |