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US3792352A Expired / Lapsed US ⏱️ 0.0 years remaining

Analog-to-digital converter utilizing different feedback effects to obtain accuracy and resolution

Assignee: Gemalto Terminals Ltd
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Filing: 1970-09-10
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Granted: 1974-02-12
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Expires: 1990-09-10
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Abstract

Abstract An analog-to-digital converter provides improved resolution without attendant loss of accuracy or speed of operation over known converters. This is achieved by providing slow-acting feedback to the integrating circuit for increasing resolution. The fast-acting feedback consists of quanta of charge of defined magnitude and the slow-acting feedback is derived from the fast feedback either by smoothing or by reducing the frequency of the quanta.

Inventors

  • 👤 E Metcalf
  • 👤 H Dorey

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 23:00
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 182 words
A digital voltmeter comprising an integrating amplifier having an input and an output, means for applying an input voltage continuously to said input; a clock pulse source, a first clock pulse counter connected to said clock pulse source and having an output provided from a low significance stage thereof; first and second feedback means both coupled to said amplifier output, said first feedback means being responsive to said low significance stage output and to said clock pulse source to make available standard units of charge when said level exceeds a predetermined limit for feedback to the amplifier input, said second feedback means being responsive thereto to provide smaller units of charge for feedback to said amplifier input; a second pulse counter having a lowest significance input and a higher significance input coupled respectively to said second and first feedback means; and sswitching means responsive to said first counter to render only the first feedback means operative until the first counter reaches a predetermined count and then to render only the second feedback means operative until the first counter reaches a final count.
Claim 2
Dependent Claim 182 words
A digital voltmeter comprising an integrating amplifier having an input and an output, means for applying an input voltage continuously to said input; a clock pulse source, a first clock pulse counter connected to said clock pulse source and having an output provided from a low significance stage thereof; first and second feedback means both coupled to said amplifier output, said first feedback means being responsive to said low significance stage output and to said clock pulse source to make available standard units of charge when said level exceeds a predetermined limit for feedback to the amplifier input, said second feedback means being responsive thereto to provide smaller units of charge for feedback to said amplifier input; a second pulse counter having a lowest significance input and a higher significance input coupled respectively to said second and first feedback means; and sswitching means responsive to said first counter to render only the first feedback means operative until the first counter reaches a predetermined count and then to render only the second feedback means operative until the first counter reaches a final count.
Claim 3
Dependent Claim 339 words
A digital voltmeter comprising the combination of an integrating circuit having an input and an output; means for applying an input volTage continuously to said circuit input; circuit means connected between said output and input of said integrating circuit for responding to the output level of said integrating circuit to control the feeding into the input of said integrating circuit standard units of charge so as to restore said level toward a datum value; timing means defining a measurement interval and a changeover time towards the end of said interval, means responsive to said timing means for applying units of charge having a frequency greater than and a size less than the standard units of charge to the input of said integrating circuit for the portion of said measurement interval between said changeover time and the end of said interval and wherein said circuit means connected between said output and input of said integrating circuit further comprises a clock pulse source; a conductive path connected to said integrating circuit input; first gate means connected between said clock pulse source and said conductive path for coupling pulses to said integrating circuit input whenever said first gate means is activated; level responsive means connected to said integrating circuit output and to said first gate means for activating said first gate means whenever the output of said integrating circuit exceeds a predetermined level; a second gate means connected to said conductive path said first and second gates being simultaneously activated by said level responsive means; and wherein said means responsive to said timing means includes a third gate connected between said clock pulse source and said first gate means; and a fourth gate with an output terminal connected to said second gate; and said apparatus further comprises a counter having an input connected to said pulse source and one output from a high significance stage thereof connected to said fourth gate; said fourth and third respectively being sequentially activated by said timing means to couple pulses to said second and first gates.
Claim 4
Dependent Claim 339 words
A digital voltmeter comprising the combination of an integrating circuit having an input and an output; means for applying an input volTage continuously to said circuit input; circuit means connected between said output and input of said integrating circuit for responding to the output level of said integrating circuit to control the feeding into the input of said integrating circuit standard units of charge so as to restore said level toward a datum value; timing means defining a measurement interval and a changeover time towards the end of said interval, means responsive to said timing means for applying units of charge having a frequency greater than and a size less than the standard units of charge to the input of said integrating circuit for the portion of said measurement interval between said changeover time and the end of said interval and wherein said circuit means connected between said output and input of said integrating circuit further comprises a clock pulse source; a conductive path connected to said integrating circuit input; first gate means connected between said clock pulse source and said conductive path for coupling pulses to said integrating circuit input whenever said first gate means is activated; level responsive means connected to said integrating circuit output and to said first gate means for activating said first gate means whenever the output of said integrating circuit exceeds a predetermined level; a second gate means connected to said conductive path said first and second gates being simultaneously activated by said level responsive means; and wherein said means responsive to said timing means includes a third gate connected between said clock pulse source and said first gate means; and a fourth gate with an output terminal connected to said second gate; and said apparatus further comprises a counter having an input connected to said pulse source and one output from a high significance stage thereof connected to said fourth gate; said fourth and third respectively being sequentially activated by said timing means to couple pulses to said second and first gates.
Claim 5
Dependent Claim 35 words
Apparatus according to claim 2 wherein said timing means comprises bistable circuit means having inputs connected to two lower significance stages of said counter and outputs connected to sequentially activate said third and fourth gates.
Claim 6
Dependent Claim 245 words
A digital voltmeter comprising an integrating circuit having an input and an output; means for applying an input voltage continuously to the input of said circuit; a clock pulse source; a first clock pulse counter connected to said source, said counter having an output provided from a low significance stage thereof; first and second circuit means both coupled between the output and input of said integrating circuit said first circuit means being responsive to the output level of said integrating circuit to provide large standard units of charge from said low significance stage of said counter to said input when the output level of said integrating circuit exceeds a predetermined level, said second circuit means being responsive to the output level of said integrating circuit to provide smaller standard units of charge from said clock pulse source to said integrating circuit input when the output level of said integrating circuit exceeds said predetermined level; switching means responsive to said first counter for activating only said first circuit means until said first counter reaches a predetermined count and for then activating only said second circuit means until said first counter reaches a final count; and a second pulse counter having a lowest significance input coupled to said second circuit means and a higher significance input coupled to said first circuit means, said second counter being operative to accumulate a pulse count from said first and second circuit means to represent the value of said input voltage.
Claim 7
Dependent Claim 245 words
A digital voltmeter comprising an integrating circuit having an input and an output; means for applying an input voltage continuously to the input of said circuit; a clock pulse source; a first clock pulse counter connected to said source, said counter having an output provided from a low significance stage thereof; first and second circuit means both coupled between the output and input of said integrating circuit said first circuit means being responsive to the output level of said integrating circuit to provide large standard units of charge from said low significance stage of said counter to said input when the output level of said integrating circuit exceeds a predetermined level, said second circuit means being responsive to the output level of said integrating circuit to provide smaller standard units of charge from said clock pulse source to said integrating circuit input when the output level of said integrating circuit exceeds said predetermined level; switching means responsive to said first counter for activating only said first circuit means until said first counter reaches a predetermined count and for then activating only said second circuit means until said first counter reaches a final count; and a second pulse counter having a lowest significance input coupled to said second circuit means and a higher significance input coupled to said first circuit means, said second counter being operative to accumulate a pulse count from said first and second circuit means to represent the value of said input voltage.

References Cited (Backward Citations)

US3296613A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-02-11 1977-08-13 1978-02-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-02-11 1981-08-13 1982-02-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-02-11 1985-08-13 1986-02-12 $7700.00 Window Closed / Lapsed

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