Timing control circuit for solid state protective relays for providing novel control of the pickup and timing circuits provided therein

Claim 1

Static relay means for use in protecting power transmission and/or distribution systems against overload conditions comprising: first means for sensing the current in the system being protected; second means coupled to said first means for converting the output of said first means into a d.c. voltage level respresentative of the current in the system being protected; timing means coupled to said second means for generating a predetermined output level after a time interval, which time interval is inversely proportional to said d.c. level; third means coupled to said second means for establishing a constant reference level which is substantially independent of the d.c. output level of said second means; fourth means having an output coupled to said timing means and being activated at its input for resetting said timing means to a zero voltage level in the sustained absence of an overload condition in the system being monitored; fifth means having at least one input terminal and an output, said input terminal coupled to said second means and said output coupled to the input of said fourth means for activating said fourth means to operate said timing means when the output level of said second means is greater than a predetermined threshold level (pick-up); sixth means coupled in common to said third means and the input of said fourth means for preventing deactivation of said fourth means when the output of said second means momentarily falls below said threshold level to permit continued operation of said timing means once said fourth means has been inactivated to enable said timing means to continue its timing function; said timing means including at least one capacitor; said fourth means including first transistor means having first and second terminals coupled across said timing means and input means for rendering said transistor means non-conductive when said fourth means is activated; said fifth means comprising second transistor means having its output terminal coupled to said third means and the input of said first transistor means and being conductive when said threshold level exceeds the instantaneous output level of said second means for activating said first transistor means to reset said timing means; a series connected zener diode means and adjustable resistor means coupled across said second means; said adjustable resistor means including a wiper arm connected directly to a control elecTrode at the input of said second transistor means; said zener diode means being adapted to conduct when the level developed by said second means is nearly equal to or greater than said threshold level; said adjustable resistor means including a portion between said zener diode means and the input of said second transistor means, with such portion having resistance value selected to limit the current drawn by said second transistor means to a safe operating value.