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US3792201A
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Time-division multiplex framing circuit
Assignee: AT&T Inc
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Filing: 1972-08-15
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Granted: 1974-02-12
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Expires: 1992-08-15
Abstract
Abstract A framing circuit for use in time-division multiplex decoders utilizes a digital ''''1'''' in the first timing slot in each frame of input data to synchronize the decoder. In the decoder, the input signal is demultiplexed into separate information channels which are separately decoded. The output signal of the first channel is then applied to a threshold detector. If the decoder is in-frame, the threshold detector will indicate that the output of the first channel is higher than the reference level of the detector. When the decoder is out-of-frame, the first channel output will vary randomly, falling below the threshold level. This will cause a signal to be generated which will block one of the timing pulses to the demultiplexer, thereby causing the relative channel locations to change by one position. This is repeated until the first framing time slot corresponds to the first decoded channel.
Inventors
- 👤 T Osborne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:39
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0617
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
195 words
A framing circuit for use in the decoder of an N channel time-division multiplex system having at least one framing bit in at least one framing time slot of the N timing slots in each frame of input data, comprising: clocking means for producing clock pulses which are synchronized with the input data; means for demultiplexing the decoding the bits in each of the N timing slots of each frame of data in response to clock pulses applied to it, the demultiplexed and decoded bits forming N separate channels of analog output signals at N output terminals; a reference voltage source having a reference voltage output uniquely associated with the channel output signal from each framing time slot; a threshold detecting means for producing a control signal when the channel output signal corresponding to each framing time slot differs from its associated reference voltage output in a predetermined sense; means for inhibiting one of the clock pulses applied to said means for demultiplexing and decoding in response to the control signal; and means for establishing an initial value for the channel output signal corresponding to each framing time slot in response to the control signal.
Claim 2
Dependent Claim
195 words
A framing circuit for use in the decoder of an N channel time-division multiplex system having at least one framing bit in at least one framing time slot of the N timing slots in each frame of input data, comprising: clocking means for producing clock pulses which are synchronized with the input data; means for demultiplexing the decoding the bits in each of the N timing slots of each frame of data in response to clock pulses applied to it, the demultiplexed and decoded bits forming N separate channels of analog output signals at N output terminals; a reference voltage source having a reference voltage output uniquely associated with the channel output signal from each framing time slot; a threshold detecting means for producing a control signal when the channel output signal corresponding to each framing time slot differs from its associated reference voltage output in a predetermined sense; means for inhibiting one of the clock pulses applied to said means for demultiplexing and decoding in response to the control signal; and means for establishing an initial value for the channel output signal corresponding to each framing time slot in response to the control signal.
Claim 3
Dependent Claim
173 words
A circuit as claimed in claim 1 wherein said means for inhibiting comprises: a bistable circuit for alternately generating high and low positive voltage levels at its output in response to a signal at its TRIGGER input and for generating a high positive level in response to a signal at its RESET input, the control signal of said threshold detector being applied to the TRIGGER input; a two-input AND gate having the output of said clocking means applied to one input and the output of said bistable circuit applied to its other input, the output of said two-input AND gate being the clock pulses applied to said means for demultiplexing and decoding; an inverter for producing an inverted version of the output of said bistable circuit element; and an inhibiting two-input NAND gate having the output of said clocking means applied to one input and the output of said inverter applied to the other input, the output of said inhibiting NAND gate being applied to the RESET input of said bistable circuit element.
Claim 4
Dependent Claim
71 words
A circuit as claimed in claim 1 wherein the one framing bit is a digital ''''1'''', the one framing time slot is the first timing slot of the frame, the channel output signal corresponding to the first timing slot is the first of N channel output signals, and the control signal of said threshold detector means is produced whenever the first channel output signal is below the first reference voltage output.
Claim 5
Dependent Claim
118 words
A circuit as claimed in claim 1 wherein the framIng bits are a digital ''''1'''' and ''''0'''' located in the first and second timing slots, respectively, the channel output signal corresponding to the first timing slot is the first of N channel output signals, the channel output signal corresponding to the second timing slot is the second of N channel output signals, the reference voltage source has first and second reference voltage outputs, and the control signal of said threshold detecting means is produced whenever the output of the first channel is below the level of the first reference voltage output and the output of the second channel is above the level of the second reference voltage output.
Claim 6
Dependent Claim
160 words
A circuit as claimed in claim 4 wherein the threshold detecting means comprises: a first comparator for generating an output whenever the voltage on its first input is larger than the voltage on its second input, the first reference voltage output being applied to the first input of said first comparator and the first channel output signal being applied to the second input; a second comparator for generating an output whenever the voltage on its first input is larger than the voltage on its second input, the second channel output signal being applied to the first input of said second comparator and the second reference voltage output being applied to the second input; and a threshold detector two-input NAND gate having the output of said first comparator applied to its first input and the output of said second comparator applied to its second input, the output of said threshold detecting NAND gate being the control signal of said framing circuit.
Claim 7
Dependent Claim
93 words
A circuit as claimed in claim 5 wherein the means for establishing an initial value comprises: an initial value inverter for generating an inverted version of the control signal at the output of said threshold detector NAND gate; a first diode having the output of said initial value inverter applied to its anode and the first channel output signal applied to its cathode; and a second diode having the output of said threshold detector NAND gate applied to its cathode and the output of said second channel output signal applied to its anode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-11 | 1977-08-13 | 1978-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-11 | 1981-08-13 | 1982-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-11 | 1985-08-13 | 1986-02-12 | $7700.00 | Window Closed / Lapsed |